LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

-- LIBRARY lpm;				Alternative Implementation von lpm_ram
-- USE lpm.lpm_components.All;


ENTITY RAM IS
PORT(
clk	: IN	std_logic;
Enabled	: IN 	std_logic;
we	: IN 	std_logic;
Adress	: IN 	std_logic_vector(3 downto 0);
data 	: INOUT	std_logic_vector(3 downto 0)
);
END RAM;

ARCHITECTURE Memory of RAM IS

COMPONENT lpm_ram_io
   GENERIC (LPM_WIDTH: INTEGER :=4;
      LPM_WIDTHAD: INTEGER := 4;
      LPM_NUMWORDS: NATURAL := 16;
      LPM_INDATA: STRING := "REGISTERED";
      LPM_ADDRESS_CONTROL: STRING := "REGISTERED";
      LPM_OUTDATA: STRING := "REGISTERED";
      LPM_FILE: STRING := "UNUSED";
      LPM_TYPE: STRING := "LPM_RAM_IO";
      LPM_HINT: STRING := "UNUSED");
   PORT (address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
      inclock, outclock: IN STD_LOGIC := '0';
      outenab : IN STD_LOGIC := '1';
      we: IN STD_LOGIC;
      dio: INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;

SIGNAL dat_sig	: std_logic_vector(3 downto 0);

BEGIN

data<=dat_sig when(Enabled='1') else "ZZZZ";
MEM: lpm_ram_io PORT MAP (Adress, clk, clk, Enabled, we, dat_sig);

END Memory;