;************************************************************************/
;*									*/
;*		Software reload Example using Timer 0			*/
;*                                                                      */
;*              Author: Peter Dannegger                                 */
;*                      danni@specs.de                                  */
;*                                                                      */
;************************************************************************/

	org 0
	jmp init
	org $+5*8+3		;reserved for interrupt vectors

init:	mov tmod, #1		;set Timer 0 mode 1
	mov tl0, #0FFh
	mov th0, #0FFh		;overflow on next cycle
	setb tr0
	clr f1sec
	mov Divider_1s, #Divider_1s_reload+1
	mov ie, #10000010b

main:	jbc f1sec main1		;test and clear
	jmp main

main1:	cpl p1.0		;change every 1 second
	jmp main


;Timebase 1 second at 12MHz: 12MHz / 12 / 62500 / 16 = 1Hz
;or			     12MHz / 12 / 4000 / 250 = 1Hz	

T0_reload		equ 62500	;or 4000
Divider_1s_reload	equ 16		;or 250

		bseg at 0
F1sec:		dbit 1

		dseg at 30h
Divider_1s:	ds 1
		cseg

curr_addr	set $

		org 000Bh

	jmp Timer0_interrupt

		org curr_addr

Timer0_interrupt:

	push psw
	clr ea			;no additional delay by other interrupts
	clr tr0			;no overflow during addition
	xch a, tl0
	add a, #low(8-T0_reload)	;stop for 8 cycle
	xch a, tl0
	xch a, th0
	addc a, #high(8-T0_reload)
	xch a, th0
	setb ea			;other interrupts enabled after next instr.
	setb tr0
	pop psw
	djnz divider_1s, ?T0I1
	mov divider_1s, #divider_1s_reload
	setb F1sec		;say to main: 1 second was finished
				;must be cleared by main
?T0I1:	reti

end