library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity xc9572board_test is port( clk : in std_logic; clk_led: out std_logic; Reset: in std_logic; we: out std_logic; oe: out std_logic; ce_addr: out std_logic_vector(0 to 3); sram_addr: out std_logic_vector(0 to 9); sram_data: inout std_logic_vector(0 to 7); --SPI-Interface spi_clk: in std_logic; AVR_MOSI: out std_logic; HS_AVR : in std_logic; HS_CPLD : out std_logic; flag : out std_logic; test : in std_logic ); end xc9572board_test; architecture Behavioral of xc9572board_test is signal status: unsigned (2 downto 0); signal we_oe_change : unsigned (2 downto 0); signal unsigned_sram_addr: unsigned (9 downto 0); signal unsigned_ce_addr: unsigned (3 downto 0); signal unsigned_sram_data: unsigned (7 downto 0); signal sig_clk_led: std_logic; --SPI-Interface signal sig_HS_CPLD :std_logic; signal sig_flag :std_logic; signal sig_Reset :std_logic; signal sig_AVR_MOSI :std_logic; signal sig_counter : unsigned (3 downto 0); begin process(Reset, clk) begin if Reset = '1' then we_oe_change <= "000"; we <= '1'; oe <= '1'; unsigned_ce_addr <= "1110"; --sig_clk_led <= '0'; --mit initialisierung kannst Du jetzt --das notverwenden status <= (others => '0'); unsigned_sram_addr <= (others => '0'); unsigned_sram_data <= (others => '0'); sig_Reset <= '0'; sig_HS_CPLD <= '0'; elsif rising_edge(clk) then case we_oe_change is when "000" => -- SCHREIBEVORGANG if unsigned_ce_addr < "1111" then if unsigned_sram_addr < "0000001000" then -- Schreibe 19 mal in SRAM if status = "000" then --State1 status <= "001"; unsigned_sram_addr <= unsigned_sram_addr + 1; --ADDR anlegen we <= '0'; oe <= '1'; elsif status = "001" then --State2 status <= "010"; unsigned_sram_data <= unsigned_sram_data;--sram_data + 1;--Datenausgabe elsif status = "010" then --State3 status <= "000"; we <= '1'; oe <= '1'; else status <= "000"; end if; else --Schleife beginnt von vorne, jedoch wird ein anderer Sram angesprochen unsigned_ce_addr(0) <= '1'; unsigned_ce_addr(1) <= unsigned_ce_addr(0); unsigned_ce_addr(2) <= unsigned_ce_addr(1); unsigned_ce_addr(3) <= unsigned_ce_addr(2); unsigned_sram_addr <= (others => '0'); status <= (others => '0'); end if; else --Schreibevorgang beendet, bereite vor auf lesen we_oe_change <= "001"; status <= (others => '0'); -- State Werte werden auf Null gesetzt unsigned_sram_addr <= (others => '0'); sram_data <= (others => 'Z'); --sram_data als Eingang unsigned_ce_addr <= "1110"; unsigned_sram_data <= (others => '0'); sig_Reset <= not sig_Reset; end if; when "001" => -- LESEVORGANG if unsigned_ce_addr < "1111" then if unsigned_sram_addr < "1111111111" and sig_HS_CPLD = '0' then --??????????????????? brauche zusätzlichen counter if status = "000" then --State1 status <= "001"; -- ADDR liegt schon an we <= '1'; oe <= '0'; sig_Reset <= '0'; unsigned_sram_data <= (others => 'Z'); --sram_data als Eingang elsif status = "001" then --State2 status <= "010"; --Daten Lesen elsif status = "010" then --State3 status <= "000"; we <= '1'; oe <= '1'; unsigned_sram_addr <= unsigned_sram_addr + 1; --ADDR anlegen, um 1 erhöhen sig_HS_CPLD <= '1'; -- Signal zum AVR, dass Daten abgeholt werden else status <= "000"; end if; elsif unsigned_sram_addr = "1111111111" and sig_HS_CPLD = '0' then --Schleife beginnt von vorne, jedoch wird ein anderer Sram angesprochen unsigned_ce_addr(0) <= '1'; unsigned_ce_addr(1) <= unsigned_ce_addr(0); unsigned_ce_addr(2) <= unsigned_ce_addr(1); unsigned_ce_addr(3) <= unsigned_ce_addr(2); unsigned_sram_addr <= (others => '0'); status <= (others => '0'); else --Tue nichts solange Daten zum AVR übertragen wurden if sig_flag = '1' then sig_HS_CPLD <= '0'; sig_Reset <= '1'; --sig_flag <= '0'; -- mögliche Fehlerquelle, da sig_flag zu process2 gehört else unsigned_ce_addr(0) <= unsigned_ce_addr(0); end if; end if; else -- Schleife ist Fertig --> RESET we_oe_change <= "000"; we <= '1'; oe <= '1'; unsigned_ce_addr <= "1110"; --sig_clk_led <= '0'; --mit initialisierung kannst Du jetzt --das notverwenden status <= (others => '0'); unsigned_sram_addr <= (others => '0'); unsigned_sram_data <= (others => '0'); sig_Reset <= '0'; sig_HS_CPLD <= '0'; end if; when others => unsigned_sram_addr <= "1111111111"; --Fehler end case; end if; end process; --SPI Process process(spi_clk,sig_Reset,HS_AVR) begin if sig_Reset = '1' then sig_flag <= '0'; sig_clk_led <= '0'; sig_counter <= (others=>'0'); sig_AVR_MOSI <= '0'; elsif rising_edge(spi_clk)and HS_AVR = '0' and sig_HS_CPLD = '1' then sig_AVR_MOSI <= unsigned_sram_data(to_integer(sig_counter)); -- 16 Bit werden übertragen sig_clk_led <= not sig_clk_led; if sig_counter = 15 then sig_flag <= '1'; -->Es darf wieder gelesen werden, Übertragung beendet sig_counter <= (others=>'0'); else sig_counter <= sig_counter + 1; end if; end if; end process; clk_led <= sig_clk_led; flag <= sig_flag; HS_CPLD <= sig_HS_CPLD; AVR_MOSI <= sig_AVR_MOSI; --unter <= std_logic_vector(sig_counter); sram_addr <= std_logic_vector(unsigned_sram_addr); ce_addr <= std_logic_vector(unsigned_ce_addr); sram_data <= std_logic_vector(unsigned_sram_data); end Behavioral;