-- Engineer: Lothar Miller -- Create Date: 09:40:35 08/28/2008 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity TopIO is Port ( sel : in STD_LOGIC; ena : in STD_LOGIC; da : in STD_LOGIC_VECTOR (3 downto 0); db : in STD_LOGIC_VECTOR (3 downto 0); do : out STD_LOGIC_VECTOR (3 downto 0)); end TopIO; architecture Behavioral of TopIO is component Komponente is Port ( sel : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (3 downto 0); data : inout STD_LOGIC_VECTOR (3 downto 0)); end component; signal doint : STD_LOGIC_VECTOR (3 downto 0); signal dbint : STD_LOGIC_VECTOR (3 downto 0); signal daint : STD_LOGIC_VECTOR (3 downto 0); begin C1: Komponente port map (sel=>sel, data=>daint, dout=>doint); daint <= da; dbint <= db; doint <= dbint when (ena='1') else (others=>'Z'); do <= doint; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; entity Komponente is Port ( sel : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (3 downto 0); data : inout STD_LOGIC_VECTOR (3 downto 0)); end Komponente; architecture Verhalten of Komponente is begin dout <= data when (sel='0') else (others=>'Z'); end Verhalten;