-- Berechnung von arithmetisch-logischen Funktionen mit einem
-- Universaladdierer und einem Komplement als Kompomenten.
-- Dateiname: ALU.vhd
-- Standard: VHDL 1993
-- Version 1.0, 26.08.08

library ieee;
use ieee.std_logic_1164.all;


entity alu is
	generic (n: natural := 8);  -- Wortbreite der ALU
	
	port (a, b	: in std_logic_vector (n-1 downto 0);
		  s	   	: in std_logic_vector (3 downto 0);
		  z	    : out std_logic_vector (3 downto 0);
		  cout  : out std_logic);
		
end entity alu;

architecture struktur of alu is

signal a_negativ		: std_logic_vector (n downto 0);
signal b_negativ 		: std_logic_vector (n downto 0);
signal a_plus_b     	: std_logic_vector (n downto 0);
signal a_minus_b    	: std_logic_vector (n downto 0);
signal b_minus_a    	: std_logic_vector (n downto 0);
signal nicht_a_minus_b	: std_logic_vector (n downto 0);
signal z1		   	    : std_logic_vector (n downto 0);


-- Komponente Komplement
component Komplement is
	generic (n: natural := 4);
	
	port (x : in std_logic_vector (n-1 downto 0);
		  z : out std_logic_vector (n-1 downto 0));
		
end component Komplement;


-- Komponente Universaladdierer
component Universaladdierer is
	generic (n : natural := 8);
	
	port (a, b : in std_logic_vector (n-1 downto 0); -- Daten
		  s	   : in std_logic; -- Umschalten zwischen Addition '0' und Subtraktion '1'
		  sum  : out std_logic_vector; -- Summe aus Daten a und b
		  cout : out std_logic); -- Übertrag

end component Universaladdierer;
	
	
	begin	-- Berechung verschiedener a und b Verknüpfungen
	P_a_negativ : 	Komplement
					generic map (n)
					port map (a, a_negativ);
	
	P_b_negativ : 	Komplement
					generic map (n)
					port map (b, b_negativ);
					
	P_a_plus_b : 	Universaladdierer
					generic map (n)
					port map (a, b, '0', a_plus_b (n-1 downto 0), a_plus_b (n));
	
	P_a_minus_b : 	Universaladdierer
					generic map (n)
					port map (a, b, '1', a_minus_b (n-1 downto 0), a_minus_b (n));
	
	P_b_minus_a : 	Universaladdierer
					generic map (n)
					port map (not a, b, '1', nicht_a_minus_b (n-1 downto 0), nicht_a_minus_b (n));
								
				
		with s select
		
			z1 <= 	(others => '0')			when 	"0000",
					'0' & a 				when 	"0001",
					'0' & b					when 	"0010",
					a_negativ				when 	"0011",
					b_negativ				when 	"0100",
					'0' & (not a)			when 	"0101",
					'0' & (not b)			when 	"0110",
					a_plus_b				when 	"0111",
					a_minus_b				when 	"1000",
					b_minus_a				when 	"1001",
					nicht_a_minus_b 		when 	"1010",
					'0' & (a or b)			when 	"1011",
					'0' & (a and b)			when 	"1100",
					'0' & (a xor b)			when 	"1101",
					'0' & (not (a xor b))	when	"1110",
					(others => '1')			when 	others;
					
	cout <= z1(n);
	z <= z1(n-1 downto 0);
end architecture struktur;