EU1KY AA
ADF4351_Reg3_t Union Reference

Union type for the structure of Register3 in ADF4351. More...

Data Fields

struct {
   uint32_t   ControlBits:3
 bit: 0.. 2 CONTROL BITS More...
 
   uint32_t   ClkDivVal:12
 bit: 3..14 12-Bit Clock Divider Value More...
 
   uint32_t   ClkDivMod:2
 bit: 15..16 Clock Divider Mode More...
 
   uint32_t   _reserved_0:1
 bit: 17 RESERVED More...
 
   uint32_t   CsrEn:1
 bit: 18 CSR Enable More...
 
   uint32_t   _reserved_1:2
 bit: 19..20 RESERVED More...
 
   uint32_t   ChargeCh:1
 bit: 21 Charge Cancelation More...
 
   uint32_t   AntibacklashW:1
 bit: 22 Antibacklash Pulse Width More...
 
   uint32_t   BandSelMode:1
 bit: 23 Band Select Clock Mode More...
 
   uint32_t   _reserved_2:8
 bit: 24..31 RESERVED More...
 
b
 
uint32_t w
 

Detailed Description

Union type for the structure of Register3 in ADF4351.

Field Documentation

uint32_t ADF4351_Reg3_t::_reserved_0

bit: 17 RESERVED

uint32_t ADF4351_Reg3_t::_reserved_1

bit: 19..20 RESERVED

uint32_t ADF4351_Reg3_t::_reserved_2

bit: 24..31 RESERVED

uint32_t ADF4351_Reg3_t::AntibacklashW

bit: 22 Antibacklash Pulse Width

struct { ... } ADF4351_Reg3_t::b
uint32_t ADF4351_Reg3_t::BandSelMode

bit: 23 Band Select Clock Mode

uint32_t ADF4351_Reg3_t::ChargeCh

bit: 21 Charge Cancelation

uint32_t ADF4351_Reg3_t::ClkDivMod

bit: 15..16 Clock Divider Mode

uint32_t ADF4351_Reg3_t::ClkDivVal

bit: 3..14 12-Bit Clock Divider Value

uint32_t ADF4351_Reg3_t::ControlBits

bit: 0.. 2 CONTROL BITS

uint32_t ADF4351_Reg3_t::CsrEn

bit: 18 CSR Enable

uint32_t ADF4351_Reg3_t::w

The documentation for this union was generated from the following file: