EU1KY AA
BACKUP.h
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1 /* Definitions for Backup and Power Control Module */
2 
3 
4 //Miscellaneous
5 
6 #define enable 0x01
7 #define disable 0x00
8 
9 #define true 0x01
10 #define false 0x00
11 
12 #define high 0x01
13 #define low 0x00
14 
15 
16 //Bitwise Operations
17 
18 #define bit_set(reg, bit_val) reg |= (1 << bit_val)
19 #define bit_clr(reg, bit_val) reg &= (~(1 << bit_val))
20 #define bit_tgl(reg, bit_val) reg ^= (1 << bit_val)
21 #define get_bit(reg, bit_val) (reg & (1 << bit_val))
22 #define get_reg(reg, msk) (reg & msk)
23 
24 
25 //Defintions for RTC clock calibration register (BKP_RTCCR)
26 
27 #define alarm_output low
28 #define second_output high
29 
30 #define set_RTC_tamper_pin_output(mode) BKP_RTCCRbits.ASOS = mode
31 #define enable_RTC_tamper_pin_output(mode) BKP_RTCCRbits.ASOE = mode
32 #define enable_RTC_clock_calibration_on_tamper_pin(mode) BKP_RTCCRbits.CCO = mode
33 #define set_RTC_clock_calibration_value(value) do{BKP_RTCCR &= 0xFFFFFF80); BKP_RTCCR |= (value & 0x7F);}while(0)
34 
35 
36 //Definitions for Backup control register (BKP_CR)
37 
38 #define set_tamper_pin_active_level(mode) BKP_CRbits.TPAL = mode
39 #define enable_tamper_pin(mode) BKP_CRbits.TPE = mode
40 
41 
42 //Definition for Backup control/status register (BKP_CSR)
43 
44 #define get_tamper_interrupt_flag() get_bit(BKP_CSR, 9)
45 #define get_tamper_event_flag() get_bit(BKP_CSR, 8)
46 #define enable_tamper_pin_interrupt(mode) BKP_CSRbits.TPIE = mode
47 #define clear_tamper_interrupt() BKP_CSRbits.CTI = 1
48 #define clear_tamper_event() BKP_CSRbits.CTE = 1
49 
50 
51 //Definition for Power control register (PWR_CR)
52 
53 #define disable_backup_domain_write_protection(mode) PWR_CRbits.DBP = mode
54 
55 #define select_PVD_level(value) do{PWR_CR &= (~(0x7 << 5)); PWR_CR |= (value << 5);}while(0)
56 
57 #define enable_PVD(mode) PWR_CRbits.PVDE = mode
58 
59 #define clear_standby_flag() PWR_CRbits.CSBF = 1
60 #define get_standby_flag() get_bit(PWR_CR, 3)
61 
62 #define clear_wakeup_flag() PWR_CRbits.CWUF = 1
63 #define get_wakeup_flag() get_bit(PWR_CR, 2)
64 
65 #define set_power_down_deep_sleep(mode) PWR_CRbits.PDDS = mode
66 
67 #define set_low_power_deep_sleep(mode) PWR_CRbits.LPDS = mode
68 
69 
70 //Definitions for Power control status register (PWR_CSR)
71 
72 #define wakeup_pin_is_a_GPIO low
73 #define wakeup_pin_is_used high
74 
75 #define use_wakeup_pin(mode) PWR_CSRbits.EWUP = mode
76 
77 #define get_PVD_output() get_bit(PWR_CSR, 2)
78 #define get_standby_flag() get_bit(PWR_CSR, 1)
79 #define get_wakeup_flag() get_bit(PWR_CSR, 0)
80 
81 //Other Definitions
82 
83 #define enable_backup_module(mode) RCC_APB1ENRbits.BKPEN = mode
84 #define enable_power_control_module(mode) RCC_APB1ENRbits.PWREN = mode