-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:50:32 11/25/2008 -- Design Name: -- Module Name: D:/XilinxISEProjects/ttd_test/calc_tb2.vhd -- Project Name: ttd_test -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: calc -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY calc_tb2 IS END calc_tb2; ARCHITECTURE behavior OF calc_tb2 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT calc PORT( clk : IN std_logic; num1 : IN std_logic_vector(19 downto 0); num2 : IN std_logic_vector(19 downto 0); num3 : IN std_logic_vector(19 downto 0); num4 : IN std_logic_vector(19 downto 0); result : OUT std_logic_vector(39 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal num1 : std_logic_vector(19 downto 0) := (others => '0'); signal num2 : std_logic_vector(19 downto 0) := (others => '0'); signal num3 : std_logic_vector(19 downto 0) := (others => '0'); signal num4 : std_logic_vector(19 downto 0) := (others => '0'); --Outputs signal result : std_logic_vector(39 downto 0); -- Clock period definitions constant clk_period : time := 1us; BEGIN -- Instantiate the Unit Under Test (UUT) uut: calc PORT MAP ( clk => clk, num1 => num1, num2 => num2, num3 => num3, num4 => num4, result => result ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for 1.25us; num1 <= "00000000000000000011"; num2 <= "00000000000000000010"; num3 <= "00000000000000000101"; num4 <= "00000000000000000110"; wait; end process; END;