library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Linearizer is PORT( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; MEM_DONE : in STD_LOGIC; MEM_VALUE : in STD_LOGIC_VECTOR(4 downto 0); MEM_VALUE_ax : out STD_LOGIC_VECTOR(4 downto 0); MEM_VALUE_bx : out STD_LOGIC_VECTOR(4 downto 0); MEM_VALUE_cx : out STD_LOGIC_VECTOR(4 downto 0); MEM_VALUE_dx : out STD_LOGIC_VECTOR(4 downto 0); MEM_START : out STD_LOGIC; RESULT : OUT STD_LOGIC_VECTOR(7 downto 0) ); end Linearizer ; architecture Behavioral of Linearizer is signal MEM_VALUE_A, MEM_VALUE_B, MEM_VALUE_C, MEM_VALUE_D : STD_LOGIC_VECTOR(4 downto 0); type main_fsm_type is (wait_for_start, start_mem_read1, mem_start1, wait_for_mem1, wait_for_mem2, wait_for_mem3, wait_for_mem4, wait_for_mem5); signal main_fsm : main_fsm_type; begin process(clk, reset) begin if reset = '1' then mem_start <= '0'; main_fsm <= wait_for_start; result <= "00000000"; elsif clk'event and clk = '1' then case main_fsm is when wait_for_start => main_fsm <= start_mem_read1; when start_mem_read1 => main_fsm <= mem_start1; MEM_START <= '1'; when mem_start1 => MEM_START <= '0'; main_fsm <= wait_for_mem1; when wait_for_mem1 => if mem_done = '1' then MEM_VALUE_A <= MEM_VALUE; main_fsm <= wait_for_mem2; end if; when wait_for_mem2 => if mem_done = '1' then MEM_VALUE_B <= MEM_VALUE; main_fsm <= wait_for_mem3; end if; when wait_for_mem3 => if mem_done = '1' then MEM_VALUE_C <= MEM_VALUE; main_fsm <= wait_for_mem4; end if; when wait_for_mem4 => if mem_done = '1' then main_fsm <= wait_for_mem5; MEM_VALUE_D <= MEM_VALUE; end if; when wait_for_mem5 => RESULT(4 downto 0) <=MEM_VALUE_A + MEM_VALUE_B + MEM_VALUE_C + MEM_VALUE_D; main_fsm <= wait_for_start; end case; end if; end process; MEM_VALUE_ax <= MEM_VALUE_A; MEM_VALUE_bx <= MEM_VALUE_B; MEM_VALUE_cx <= MEM_VALUE_C; MEM_VALUE_dx <= MEM_VALUE_D; end Behavioral;