-------------------------------------------------------------------------------- -- Engineer: Lothar Miller -- -- Create Date: 14:14:03 01/12/2009 -- Design Name: Frequenzmesser -- Module Name: F:/Projekte/FPGA/Frequenzmesser/tb_Frequenzmesser.vhd -- Project Name: Frequenzmesser -- VHDL Test Bench Created by ISE for module: Frequenzmesser -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb_Frequenzmesser_vhd IS END tb_Frequenzmesser_vhd; ARCHITECTURE behavior OF tb_Frequenzmesser_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Frequenzmesser PORT( clk8M : IN std_logic; sig : IN std_logic; cnt : OUT std_logic_vector(15 downto 0) ); END COMPONENT; --Inputs SIGNAL clk8M : std_logic := '0'; SIGNAL sig : std_logic := '0'; --Outputs SIGNAL cnt : std_logic_vector(15 downto 0); BEGIN -- Instantiate the Unit Under Test (UUT) uut: Frequenzmesser PORT MAP( clk8M => clk8M, sig => sig, cnt => cnt ); clk8M <= not clk8M after 62.5 ns; -- 8 MHz sig <= not sig after 12.5 us; -- 40 kHz END;