-- Clearable loadable enablable counter LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ClockModulator IS PORT ( ClockIn : IN STD_LOGIC; Reset_N : IN STD_LOGIC; ClockModulation : IN INTEGER RANGE 0 TO 9; ClockDelay : IN INTEGER RANGE 0 TO 9; ClockOut : OUT STD_LOGIC ); END ClockModulator; ARCHITECTURE Behaviorial OF ClockModulator IS SIGNAL signalcount10 : INTEGER RANGE 0 TO 9; SIGNAL signalclock : STD_LOGIC; SIGNAL signalenable : STD_LOGIC; BEGIN PROCESS (ClockIn, Reset_N, ClockModulation, ClockDelay) BEGIN IF Reset_N = '0' THEN signalcount10 <= 0; signalclock <= '0'; signalenable <= '0'; ELSIF (ClockIn'EVENT AND ClockIn = '1') THEN IF signalenable = '1' THEN IF signalcount10 = ClockModulation THEN signalclock <= '1'; END IF; ELSE IF signalcount10 = ClockDelay THEN signalcount10 <= 0; --Counter-Reset funktioniert nicht signalenable <= '1'; END IF; END IF; IF signalcount10 = 9 THEN signalcount10 <= 0; signalclock <= '0'; ELSE signalcount10 <= signalcount10 + 1; END IF; END IF; END PROCESS; ClockOut <= signalclock; END Behaviorial;