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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

use IEEE.NUMERIC_STD.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity toplevel is
	Port (	LEDs_out					:			out	Std_Logic_Vector (7 downto 0);
				DIP_Switches			:			in		Std_Logic_Vector (7 downto 0);
--				Push_Button_Reset		:			in		Std_Logic;
				reset						:			in		Std_Logic;
--				RS232						:			inout Std_Logic_Vector (xxx);
				
				CLK						:			in		Std_Logic);
end toplevel;

architecture Behavioral of toplevel is

signal LEDs_in							:			Std_Logic_Vector (7 downto 0) := (others => '0');
signal count							:			integer range 0 to (125000000/2-1);
signal signed_DIP						:			SIGNED(7 downto 0);

begin

process(reset,CLK)
begin
	if reset = '1' then
		count <= 0;
		LEDs_in <= X"01";
		signed_DIP <= SIGNED(DIP_Switches); 
	elsif rising_edge(CLK) then
		if count < ((125000000 / signed_DIP) - 1) then
			count <= count +1;
		else
			LEDs_in <= LEDs_in(6 downto 0) & LEDs_in(7);
			count <= 0;
		end if;
	end if;
end process;


LEDs_out <= LEDs_in;

end Behavioral;