library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Mem_interface is
    Port ( 
		--Load/Store Signale
	 	address : in std_logic_vector(31 downto 0);
           	data_wr : in std_logic_vector(31 downto 0);
           	data_rd : out std_logic_vector(31 downto 0);
           	wr : in std_logic;
           	rd : in std_logic;
		 
		 --Fetch-Signale
           	pc : in std_logic_vector(31 downto 0);
           	fetch_valid : out std_logic;
           	instruction : out std_logic_vector(31 downto 0);

		 --allgemeine Ausgangs-Signale (Memory)
		 rd_out: out std_logic;
		 wr_out: out std_logic;
		 memory_address : out std_logic_vector(31 downto 0);
		 mem_wr_data : out std_logic_vector(31 downto 0);

		 --allgemeine Signale (Pipeline)
		 mem_stall_out: out std_logic;

		 --FlashROM-Signale
           	 flash_rd : in std_logic_vector(31 downto 0);
		 flash_ready: in std_logic;
		 cs_flash: out std_logic;

		 --SDRAM-Signale
		 sdram_ready : in std_logic;
		 sdram_rd : in std_logic_vector(31 downto 0);
		 cs_sdram: out std_logic;

		 --LCD-Signale
		 LCD_ready: in std_logic;
		 cs_lcd: out std_logic;

		 --Takt, Reset, LEDs
		 clk : in std_logic;
		 reset : in std_logic;
		 LED_out : out std_logic_vector(7 downto 0);
		 brake : in std_logic;
		 flash_ready_out : out std_logic;

	   	 --Programcounter
		 copy_count : in std_logic_vector(31 downto 0);

		 --BootLoader-Data
		 bl_data : in std_logic_vector(31 downto 0));

end Mem_interface;

--Adressbereiche:
--fetch:
--0-0x3fff		:FlashROM
--0x3fff->		:SDRAM
--
--load/store:
--				store:	load:
--0-0x7f			LCD		Flash
--0x80			LEDs		Flash
--0x90-0x9f		RS232	RS232 -- nur für die RS232 Gruppe
--0x90-0x9f		PS2		PS2   -- nur für die PS2 Gruppe
--0x90-0x9f		SPI		SPI   -- nur für die SPI Gruppe
--0xa0-0x3fff		SDRAM	Flash
--0x3fff->		SDRAM	SDRAM


architecture Behavioral of Mem_interface is

constant sel_SDRAM	: std_logic_vector(2 downto 0) := "000"; 
constant sel_FLASH	: std_logic_vector(2 downto 0) := "001"; 
constant sel_RS232	: std_logic_vector(2 downto 0) := "010"; 
constant sel_PS2	: std_logic_vector(2 downto 0) := "011"; 
constant sel_SPI	: std_logic_vector(2 downto 0) := "100";


signal data_sel: std_logic_vector(2 downto 0);
signal data_save: std_logic_vector(31 downto 0);

begin

flash_ready_out <= flash_ready;


process (clk, brake)
begin
 if clk'event and clk='1' then
	data_rd<=data_save; -- Taktsynchrone Ausgabe der gelesenen Daten
	
	
	if brake='1' then
		mem_stall_out <= '1'; -- Pipeline aufhalten
		mem_wr_data <= bl_data;	
  	else
  		mem_stall_out <= '0'; -- Pipeline weiterlaufen lassen
		mem_wr_data <= data_wr;
 	end if;

 end if;
end process;


process (flash_rd,sdram_rd,data_sel)
begin
  -- Asynchrones Puffern gelesener Daten
  case data_sel is
    when sel_SDRAM =>
       instruction <= sdram_rd;
       data_save <= sdram_rd;
    when sel_FLASH =>
       instruction <= flash_rd;
       data_save <= flash_rd;
    when others =>
		null;
  end case;
end process;

	
process (address,pc,rd,wr,flash_ready,sdram_ready,LCD_ready,copy_count)
begin
 -- Verarbeitung eingehender Speicherzugriffe
 if rd='1' or wr='1' then -- load oder store
   	fetch_valid<='0';

	--D, S
	if brake = '0' then
		memory_address<=address;
		mem_stall_out<='0';
	else
		if (copy_count > 16383) then		-- Wenn Wert größer als 3FFF
			memory_address<=copy_count;
			mem_stall_out<='1';
		end if;
	end if;
	--Ende			

	cs_sdram <='0';
	cs_LCD <='0';
	cs_flash <= '0';
	rd_out<='0';
	wr_out<='0';
	if wr='1' then
		wr_out<='1';
		if address(31 downto 7)=conv_std_logic_vector(0,25) then
		--schreiben auf LCD
			 if LCD_ready='0' then
	  			mem_stall_out<='1';
	  			cs_LCD <='1';
			 end if;
		else
		--schreiben in SDRAM
	       if sdram_ready='0' then
	   		mem_stall_out<='1';
	  			cs_sdram <='1';
		   end if;
		end if;
	else
		rd_out<='1';

		--D,S
		if brake = '0' then
			if address(31 downto 14)=conv_std_logic_vector(0,18) then  --Von Adresse lesen
			--lesen aus Flash
				 if flash_ready='0' then
	  				mem_stall_out<='1';
	  				cs_flash <='1';
				 end if;
		   	 data_sel<=sel_FLASH;
			else
		 	 --lesen aus SDRAM
	      	 if sdram_ready='0' then
	   			mem_stall_out<='1';
	  				cs_sdram <='1';
				 end if;
		   	 data_sel<=sel_SDRAM;
			end if;
		else 
			if copy_count(31 downto 14)=conv_std_logic_vector(0,18) then --Von Counter lesen
			--lesen aus Flash
				 if flash_ready='0' then
	  				mem_stall_out<='1';
	  				cs_flash <='1';
				 end if;
		   	 data_sel<=sel_FLASH;
			else
		 	 --lesen aus SDRAM
	      	 if sdram_ready='0' then
	   			mem_stall_out<='1';
	  				cs_sdram <='1';
				 end if;
		   	 data_sel<=sel_SDRAM;
			end if;
	    end if;
	end if;
	--Ende D,S
 else
 	-- fetch
	
	--D,S
	if brake = '0' then
		memory_address<=PC;
		mem_stall_out<='0';
	else
		memory_address<=copy_count;
	end if;
	--Ende D,S
	
	rd_out<='1';
	wr_out<='0';
	cs_sdram <='0';
	cs_LCD <='0';
	cs_flash<='0';
	
	fetch_valid<='0';

	--S, D
	if brake = '0' then
		if pc(31 downto 14)=conv_std_logic_vector(0,18) then
			--fetch aus Flash
		 	data_sel<=sel_FLASH;
		 	if flash_ready='0' then
				fetch_valid<='0';
				cs_flash <='1';
		 	else
				fetch_valid<='1';
		 	end if;
		else
	    		--fetch aus SDRAM
	    		data_sel<=sel_SDRAM;
	    		if sdram_ready='0' then
	 			fetch_valid<='0';
				cs_sdram <='1';
			 else
				fetch_valid<='1';
			 end if;
		end if;
	else
		if copy_count(31 downto 14)=conv_std_logic_vector(0,18) then
			--fetch aus Flash
		 	data_sel<=sel_FLASH;
		 	if flash_ready='0' then
				fetch_valid<='0';
				cs_flash <='1';
		 	else
				fetch_valid<='1';
		 	end if;
		else
	    		--fetch aus SDRAM
	    		data_sel<=sel_SDRAM;
	    		if sdram_ready='0' then
	 			fetch_valid<='0';
				cs_sdram <='1';
			 else
				fetch_valid<='1';
			 end if;
		end if;
	end if;
	--Ende D,S

 end if;
end process;


process (clk, reset)
begin
  -- Schreiben des LCDs
  if reset='1' then
    LED_out<="11111111";
  elsif clk'event and clk='1' then
    if address=conv_std_logic_vector(128,32) and wr='1' then
	   LED_out <=  not data_wr(7 downto 0);
    end if;
  end if;
end process; 

end Behavioral;