| Uhr Project Status (02/06/2009 - 20:19:42) | |||
| Project File: | Uhr.ise | Current State: | Programming File Generated |
| Module Name: | anzeige |
|
No Errors |
| Target Device: | xc3s700an-4fgg484 |
|
No Warnings |
| Product Version: | ISE 10.1.03 - WebPACK |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
All Constraints Met |
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Timing Report) |
| Uhr Partition Summary | [-] | |||
| No partition information was found. | ||||
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 127 | 11,776 | 1% | ||
| Number of 4 input LUTs | 189 | 11,776 | 1% | ||
| Logic Distribution | |||||
| Number of occupied Slices | 142 | 5,888 | 2% | ||
| Number of Slices containing only related logic | 142 | 142 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 142 | 0% | ||
| Total Number of 4 input LUTs | 218 | 11,776 | 1% | ||
| Number used as logic | 189 | ||||
| Number used as a route-thru | 29 | ||||
| Number of bonded IOBs | |||||
| Number of bonded | 20 | 372 | 5% | ||
| Number of BUFGMUXs | 1 | 24 | 4% | ||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Fr 6. Feb 20:18:44 2009 | 0 | 0 | 3 Infos | |
| Translation Report | Current | Fr 6. Feb 20:18:52 2009 | 0 | 0 | 0 | |
| Map Report | Current | Fr 6. Feb 20:18:59 2009 | 0 | 0 | 2 Infos | |
| Place and Route Report | Current | Fr 6. Feb 20:19:21 2009 | 0 | 0 | 0 | |
| Static Timing Report | Current | Fr 6. Feb 20:19:32 2009 | 0 | 0 | 2 Infos | |
| Bitgen Report | Current | Fr 6. Feb 20:19:40 2009 | 0 | 0 | 0 | |