static Cyg_ErrNo spi_write( cyg_io_handle_t handle, const void *buf, 
                            cyg_uint32 *len)
{
  dbguPrint("Start von SPI_WRITE\n");
  xPrintf("Status_Register %lX\n", AT91C_BASE_SPI1->SPI_SR);



  (((struct spi_buf_t*)buf)->driverMode) = 1;
  xPrintf("-->spi_write(): channel: %d, len: %d , txbuf: %d, rxbuf: %d.. ?",
                        ((struct spi_buf_t*)buf)->channelNum,
                        ((struct spi_buf_t*)buf)->packetSize,
                        ((struct spi_buf_t*)buf)->txBuffer,
                        ((struct spi_buf_t*)buf)->rxBuffer);

//  AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA2;
  cyg_mutex_lock(&mut_SpiHW);
//  AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA2;

  if ( (((struct spi_buf_t*)buf)->driverMode)==POLLING_MODE )
  {
 while ( !((AT91C_BASE_SPI1->SPI_SR) & AT91C_SPI_ENDRX ) );  //!!! spi hardware muss frei sein! 
    cyg_drv_interrupt_mask( spi_irqConfig.int_vector);

//    AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA2;
    dbguPrint("vor transmit\n");
    spiTransmit( ((struct spi_buf_t*)buf)->channelNum, ((struct spi_buf_t*)buf)->txBuffer, 
                 ((struct spi_buf_t*)buf)->rxBuffer, 
                 ((struct spi_buf_t*)buf)->packetSize);
    dbguPrint("nach transmit\n");
    AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA2;

    while ( !((AT91C_BASE_SPI1->SPI_SR) & AT91C_SPI_ENDRX ) );  //!!! ENDRX ist wichtig! 

//    AT91C_BASE_PIOA->PIO_CODR = AT91C_PIO_PA2;
    cyg_mutex_unlock(&mut_SpiHW);
//    AT91C_BASE_PIOA->PIO_SODR = AT91C_PIO_PA2;
  }
  else
    if ( (((struct spi_buf_t*)buf)->driverMode)==INTERRUPT_MODE )
    {
      dbguPrint("Interrupt Mode");
      cyg_drv_interrupt_unmask( spi_irqConfig.int_vector);
      spiTransmit( ((struct spi_buf_t*)buf)->channelNum, ((struct spi_buf_t*)buf)->txBuffer, 
                   ((struct spi_buf_t*)buf)->rxBuffer, 
                   ((struct spi_buf_t*)buf)->packetSize);
    }
    else return EINVAL; */

  dbguPrint("Ende von SPI_WRITE\n");
  xPrintf("Status_Register %lX\n", AT91C_BASE_SPI1->SPI_SR);
 
  return ENOERR;

    
}

void spiTransmit(char channel, char *txBuffer, char *rxBuffer, unsigned short length)
{
//    unsigned int status; 
//    unsigned int val;

    dbguPrint("Start von Transmit\n");
    AT91PS_SPI pSPI = AT91C_BASE_SPI1; // pointer to a SPI controller

    spiTransLength = 0;

    if (spiRole == SPI_ROLE_MASTER) {
        //set the rigth chip select 
        AT91F_SPI_CfgPCS(AT91C_BASE_SPI1, ~((char)1<<channel) );   

        //disable 
        pSPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;

        //* Initialize the Transmit and Receive Pointer
        pSPI->SPI_TPR = (unsigned int) txBuffer ;
        //pSPI->SPI_RPR = (unsigned int) rxBuffer ;

        //* Intialize the Transmit and Receive Counters
        //pSPI->SPI_RCR = (unsigned int)length;
        pSPI->SPI_TCR = (unsigned int)length;

        // trigger interrupt when the last byte was received!!
        pSPI->SPI_IER = AT91C_SPI_RXBUFF | AT91C_SPI_MODF;

        //enable transmitter and receiver
        AT91C_BASE_SPI1->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;

    } 
    else 
    {
        //SPI Slave
        pTxBuffer = txBuffer;
        pRxBuffer = rxBuffer;
        txRxLength = length;

        //write the first byte to the transmit register
        AT91C_BASE_SPI1->SPI_TDR = (unsigned int) pTxBuffer[0];

        rxIndex = 0;
        txIndex = 0;

        //enable the Transmit and Receive Data Interrupts
        pSPI->SPI_IER = AT91C_SPI_TDRE;
        pSPI->SPI_IER = AT91C_SPI_RDRF;

        //unblock the master
        //spiSetRts(FALSE);
    }
}