library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; entity reg2 is port ( clk : in std_logic; reset_n : in std_logic; clk_in : in std_logic; LED : out std_logic_vector(7 downto 0)); end reg2; architecture VERHALTEN of reg2 is signal clk_new : std_logic; signal r_l : std_logic; signal shift : std_logic_vector (7 downto 0); begin links:process (clk, reset_n) variable temp : std_logic; begin if reset_n = '0' then shift <= "00000001"; temp := '1'; elsif clk ='1' and clk'event then clk_new <=clk_in; if clk_in = '0'and clk_new ='1' then if r_l = '0' then shift(7 downto 1) <= shift(6 downto 0) ; else shift(6 downto 0) <= shift(7 downto 1); end if; if shift = "11111111" then r_l <='1'; shift(7)<= '0'; shift(7 downto 1) <= shift(6 downto 0) ; elsif shift="00000000" then shift(0)<= '1'; end if; end if; LED <= shift; end if; end process links; end VERHALTEN;