library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



--INVERTIERTES SIGNAL !!!!

entity GetSyncAndBit is
    Port ( sig : in  STD_LOGIC;  --demoduliertes DCF-Signal
	   clk: in STD_LOGIC;
	   res: in STD_LOGIC;
           segm: out  STD_LOGIC_VECTOR (7 downto 0);
	   segm2: out STD_LOGIC_VECTOR (7 downto 0));
			  
end GetSyncAndBit;

architecture Behavioral of GetSyncAndBit is

signal count: std_logic_vector (27 downto 0) ;
signal count_bit: std_logic_vector (27 downto 0);
signal sync: std_logic; --Sync Signal zum erkennen der 59. Sekunde
signal current: std_logic; --Das aktuelle Bit



begin
--Sync und aktuelles Bit zuweisen
sync <= '1' when count>"11100100111000011100000000" else '0';  --Sync = 1 wenn Pause > 1,2 s
current <= '1' when count_bit>"10110111000110110000000" else '0'; --current = 1 wenn High > 120 ms   
 
--Anzeige auf 7-Segment								    
segm <= "00000110" when sync = '1' else "00111111";  --Sync-Signal anzeigen
segm2<="00000110" when current = '1' else "00111111"; --aktuelles Bit anzeigen


TIMER: process(clk, res)
begin
if res='0' or sig='0' then --Zähler rücksetzen
count<=(others=>'0');
elsif clk='1' and clk'event and sig='1' then
count<=(count+1); --Zähler für Sync
end if;

if clk='1' and clk'event and sig='0' then
count_bit<=(count_bit+1); --Zähler für Current
end if;

if sig='1' then
count_bit<=(others=>'0'); --Zähler rücksetzen
end if;

end process;





end Behavioral;