-- VHDL Architecture my_project_lib.crpt_adapter.fertig2
--
-- Created:
--          by - carcom.UNKNOWN (CAE-P11)
--          at - 10:44:36 22.04.2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
--VHDL Entity my_project_lib.crpt_adapter.arch_name
--
-- Created:
--          by - carcom.UNKNOWN (CAE-P11)
--          at - 10:43:17 22.04.2009
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY crpt_adapter IS
 
   PORT( 
   
        -- general inputs
        CRPT_Clk          : IN     std_logic;
        CRPT_Rst          : IN     std_logic;
        -- Interface towards crypto device
        CRPT_message      : OUT    std_ulogic_vector (511 DOWNTO 0);
        CRPT_message_len  : OUT    std_ulogic_vector (9 DOWNTO 0);
        CRPT_message_rdy  : in    std_ulogic;       
        CRPT_next_message : IN     std_ulogic;
        CRPT_result       : in     std_ulogic_vector (255 DOWNTO 0);
        CRPT_result_rdy   : IN     std_ulogic;
        crpt_next_result  : out     std_ulogic;    
        
        -- DO NOT EDIT BELOW THIS LINE ---------------------
        -- Bus protocol ports, do not add or delete.
        FSL_Clk           : IN     std_logic;
        FSL_Rst           : IN     std_logic;
        FSL_S_Clk         : OUT    std_logic;
        FSL_S_Read        : OUT    std_logic;
        FSL_S_Data        : IN     std_ulogic_vector (0 TO 31); 
        FSL_S_Control     : IN     std_logic;
        FSL_S_Exists      : IN     std_logic;
        FSL_M_Clk         : OUT    std_logic;
        FSL_M_Write       : in    std_logic; --geändert von out auf in
        FSL_M_Data        : inout    std_ulogic_vector (0 TO 31);--haben wir geändert von logic in u logic und auf in 
        FSL_M_Control     : in    std_logic;--geändert auf in
        FSL_M_Full        : out     std_logic --out statt in neu
      -- H                  :  in    std_ulogic_vector (0 TO 31);         
        -- DO NOT EDIT ABOVE THIS LINE ---------------------
     );
  
  -- Declarations
  
   
  attribute SIGIS : string;
  attribute SIGIS of FSL_Clk   : signal is "Clk";
  attribute SIGIS of FSL_S_Clk : signal is "Clk";
  attribute SIGIS of FSL_M_Clk : signal is "Clk";
   
   
  
END ENTITY crpt_adapter;

ARCHITECTURE fertig2 OF crpt_adapter IS

signal m: std_ulogic_vector (0 to 255);
  signal Read_cycle2 : integer:=0 ;
  signal Time_out2 : integer:=0 ;
 

  TYPE STATE_TYPE IS (
     HW,
     Adapter,
     MP_Ubergabe
  );

  -- Declare current and next state signals
  SIGNAL current_state : STATE_TYPE;
  SIGNAL next_state : STATE_TYPE;

BEGIN
 clocked_proc : PROCESS ( 
CRPT_Clk,
CRPT_Rst
)
-----------------------------------------------------------------
variable c: integer := 0;
BEGIN
IF (CRPT_Rst = '1') THEN
current_state <= HW;
ELSIF (CRPT_Clk'EVENT AND CRPT_Clk = '1') THEN
-- test state register statements
current_state <= next_state;
ELSIF Read_Cycle2 >0  THEN
-- test state register statements
c:=c+1;
Time_out2 <=c;
-- Combined Actions

END IF;
END PROCESS clocked_proc;

-----------------------------------------------------------------
nextstate_proc : PROCESS ( 
CRPT_next_message,
CRPT_result_rdy,
Read_cycle2,
FSL_M_Control,   
current_state
)
-----------------------------------------------------------------

BEGIN
CASE current_state IS
WHEN HW => 
IF ((CRPT_result_rdy'event) and (CRPT_result_rdy='1')) THEN 
  next_state <= Adapter;
ELSE
  next_state <= HW;
END IF;
WHEN Adapter => 
IF ((CRPT_result_rdy'event) and (CRPT_result_rdy='0'))         
   THEN 
  next_state <= HW;
                                 
   Elsif  (FSL_M_Control='1')and( Read_cycle2=0) then       
  next_state <= MP_Ubergabe;
ELSE
  next_state <= Adapter;
END IF;
WHEN MP_Ubergabe => 
IF ((CRPT_result_rdy = '1') and
   (CRPT_result_rdy'event)and (Read_cycle2=7))then
  
  next_state <= Adapter;

ELSIF  (Read_cycle2=7) THEN                               
  next_state <= HW;

END IF;
WHEN OTHERS =>
next_state <= HW;
END CASE;

END PROCESS nextstate_proc;
--_____________________________________________________________________________


states : process (

current_state,
CRPT_Clk,

CRPT_result_rdy
)
variable l: integer := 0;

Begin
CASE current_state IS
WHEN Adapter => 

 m <= CRPT_result; 
 crpt_next_result<='1';             
    
WHEN MP_Ubergabe => 
 

FSL_M_Full<='0'  ;  

FSL_M_Data<=m(((32*L)+0) to ((32*L)+31));

L:= L + 1;
 
if (FSL_M_data="00000000000000000000000000000001")then    
 FSL_M_Full<='1';
   
  FSL_M_Full<='1';
elsif (L = 8) then
L:=0;


end if;
Read_Cycle2 <= L;

When HW =>
Read_Cycle2 <=0;
L:=0;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS states;     
END ARCHITECTURE fertig2;