cpldfit:  version J.33                              Xilinx Inc.
                                  Fitter Report
Design Name: minilog                             Date:  7- 8-2009, 10:39AM
Device Used: XC9572-7-TQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
39 /72  ( 54%) 102 /360  ( 28%) 79 /144 ( 55%)   29 /72  ( 40%) 53 /72  ( 74%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           8/18        9/36        9          14/90       8/18
FB2          16/18       21/36       21          32/90       7/18
FB3          10/18       18/36       18          20/90       7/18
FB4           5/18       31/36       31          36/90       1/18
             -----       -----                   -----       -----     
             39/72       79/144                 102/360     23/72 

* - Resource is exhausted

** Global Control Resources **

Signal 'clk_80' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   29          29    |  I/O              :    52      66
Output        :   23          23    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     53          53

** Power Data **

There are 39 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 23 Outputs **

Signal                                              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                                Pts   Inps          No.  Type    Use     Mode Rate State
RAM_DATA<4>                                         2     2     FB1_1   16   I/O     O       STD  FAST 
RAM_DATA<3>                                         2     2     FB1_3   18   I/O     O       STD  FAST 
RAM_DATA<2>                                         2     2     FB1_5   14   I/O     O       STD  FAST 
RAM_DATA<5>                                         2     2     FB1_8   17   I/O     O       STD  FAST 
RAM_DATA<6>                                         2     2     FB1_10  28   I/O     O       STD  FAST 
RAM_DATA<7>                                         2     2     FB1_13  36   I/O     O       STD  FAST 
RAM_OE                                              1     1     FB1_15  29   I/O     O       STD  FAST RESET
RAM_WE                                              1     2     FB1_16  39   I/O     O       STD  FAST RESET
RAM_ADDR<0>                                         2     3     FB2_1   87   I/O     O       STD  FAST RESET
RAM_ADDR<1>                                         2     3     FB2_4   93   I/O     O       STD  FAST RESET
RAM_ADDR<10>                                        2     3     FB2_6   96   I/O     O       STD  FAST RESET
RAM_ADDR<11>                                        2     3     FB2_8   97   I/O     O       STD  FAST RESET
RAM_ADDR<2>                                         2     3     FB2_12  6    I/O     O       STD  FAST RESET
RAM_ADDR<3>                                         2     3     FB2_15  11   I/O     O       STD  FAST RESET
RAM_ADDR<4>                                         2     3     FB2_17  12   I/O     O       STD  FAST RESET
RAM_ADDR<5>                                         2     3     FB3_2   32   I/O     O       STD  FAST RESET
RAM_ADDR<6>                                         2     3     FB3_4   50   I/O     O       STD  FAST RESET
RAM_ADDR<7>                                         2     3     FB3_7   54   I/O     O       STD  FAST RESET
RAM_ADDR<8>                                         2     3     FB3_10  60   I/O     O       STD  FAST RESET
RAM_ADDR<9>                                         2     3     FB3_13  63   I/O     O       STD  FAST RESET
RAM_DATA<0>                                         2     2     FB3_16  65   I/O     O       STD  FAST 
RAM_DATA<1>                                         2     2     FB3_18  59   I/O     O       STD  FAST 
TRIGGER_N                                           25    25    FB4_5   67   I/O     O       STD  FAST 

** 16 Buried Nodes **

Signal                                              Total Total Loc     Pwr  Reg Init
Name                                                Pts   Inps          Mode State
address<9>                                          2     12    FB2_5   STD  RESET
address<8>                                          2     11    FB2_7   STD  RESET
address<7>                                          2     10    FB2_9   STD  RESET
address<6>                                          2     9     FB2_10  STD  RESET
address<5>                                          2     8     FB2_11  STD  RESET
address<4>                                          2     7     FB2_13  STD  RESET
address<3>                                          2     6     FB2_14  STD  RESET
address<11>                                         2     14    FB2_16  STD  RESET
address<10>                                         2     13    FB2_18  STD  RESET
address<2>                                          2     5     FB3_14  STD  RESET
address<1>                                          2     4     FB3_15  STD  RESET
address<0>                                          2     3     FB3_17  STD  RESET
in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT  1     2     FB4_15  STD  
divider<0>                                          3     4     FB4_16  STD  RESET
countUP                                             3     5     FB4_17  STD  RESET
divider<1>                                          4     5     FB4_18  STD  RESET

** 30 Inputs **

Signal                                              Loc     Pin  Pin     Pin     
Name                                                        No.  Type    Use     
trigger_data<6>                                     FB1_2   13   I/O     I
trigger_data<3>                                     FB1_6   15   I/O     I
clk_div<0>                                          FB1_7   25   I/O     I
clk_80                                              FB1_9   22~  GCK/I/O GCK
trigger_mask<1>                                     FB1_12  33   I/O     I
trigger_data<4>                                     FB1_17  30   I/O     I
trigger_mask<4>                                     FB2_2   94   I/O     I
in_data<2>                                          FB2_3   91   I/O     I
trigger_mask<0>                                     FB2_5   95   I/O     I
clk_div<1>                                          FB2_10  1    I/O     I
trigger_mask<2>                                     FB2_16  10   I/O     I
trigger_mask<7>                                     FB3_5   35   I/O     I
in_data<1>                                          FB3_8   37   I/O     I
trigger_mask<6>                                     FB3_9   42   I/O     I
in_data<6>                                          FB3_11  52   I/O     I
trigger_data<2>                                     FB3_12  61   I/O     I
ram_read                                            FB3_14  55   I/O     I
in_data<5>                                          FB3_15  56   I/O     I
in_data<4>                                          FB3_17  58   I/O     I
in_data<0>                                          FB4_2   64   I/O     I
clear                                               FB4_4   72   I/O     I
buffer_off                                          FB4_6   76   I/O     I
trigger_data<1>                                     FB4_7   77   I/O     I
trigger_mask<5>                                     FB4_8   68   I/O     I
trigger_mask<3>                                     FB4_9   70   I/O     I
in_data<3>                                          FB4_10  81   I/O     I
trigger_data<0>                                     FB4_11  74   I/O     I
trigger_data<7>                                     FB4_14  78   I/O     I
in_data<7>                                          FB4_15  89   I/O     I
trigger_data<5>                                     FB4_17  90   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               9/27
Number of signals used by logic mapping into function block:  9
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
RAM_DATA<4>           2       0     0   3     FB1_1   16    I/O     O
(unused)              0       0     0   5     FB1_2   13    I/O     I
RAM_DATA<3>           2       0     0   3     FB1_3   18    I/O     O
(unused)              0       0     0   5     FB1_4   20    I/O     
RAM_DATA<2>           2       0     0   3     FB1_5   14    I/O     O
(unused)              0       0     0   5     FB1_6   15    I/O     I
(unused)              0       0     0   5     FB1_7   25    I/O     I
RAM_DATA<5>           2       0     0   3     FB1_8   17    I/O     O
(unused)              0       0     0   5     FB1_9   22    GCK/I/O GCK
RAM_DATA<6>           2       0     0   3     FB1_10  28    I/O     O
(unused)              0       0     0   5     FB1_11  23    GCK/I/O 
(unused)              0       0     0   5     FB1_12  33    I/O     I
RAM_DATA<7>           2       0     0   3     FB1_13  36    I/O     O
(unused)              0       0     0   5     FB1_14  27    GCK/I/O 
RAM_OE                1       0     0   4     FB1_15  29    I/O     O
RAM_WE                1       0     0   4     FB1_16  39    I/O     O
(unused)              0       0     0   5     FB1_17  30    I/O     I
(unused)              0       0     0   5     FB1_18  40    I/O     

Signals Used by Logic in Function Block
  1: countUP            4: in_data<4>         7: in_data<7> 
  2: in_data<2>         5: in_data<5>         8: in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT 
  3: in_data<3>         6: in_data<6>         9: ram_read 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
RAM_DATA<4>          ...X...X................................ 2       2
RAM_DATA<3>          ..X....X................................ 2       2
RAM_DATA<2>          .X.....X................................ 2       2
RAM_DATA<5>          ....X..X................................ 2       2
RAM_DATA<6>          .....X.X................................ 2       2
RAM_DATA<7>          ......XX................................ 2       2
RAM_OE               ........X............................... 1       1
RAM_WE               X.......X............................... 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               21/15
Number of signals used by logic mapping into function block:  21
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
RAM_ADDR<0>           2       0     0   3     FB2_1   87    I/O     O
(unused)              0       0     0   5     FB2_2   94    I/O     I
(unused)              0       0     0   5     FB2_3   91    I/O     I
RAM_ADDR<1>           2       0     0   3     FB2_4   93    I/O     O
address<9>            2       0     0   3     FB2_5   95    I/O     I
RAM_ADDR<10>          2       0     0   3     FB2_6   96    I/O     O
address<8>            2       0     0   3     FB2_7   3     GTS/I/O (b)
RAM_ADDR<11>          2       0     0   3     FB2_8   97    I/O     O
address<7>            2       0     0   3     FB2_9   99    GSR/I/O (b)
address<6>            2       0     0   3     FB2_10  1     I/O     I
address<5>            2       0     0   3     FB2_11  4     GTS/I/O (b)
RAM_ADDR<2>           2       0     0   3     FB2_12  6     I/O     O
address<4>            2       0     0   3     FB2_13  8     I/O     (b)
address<3>            2       0     0   3     FB2_14  9     I/O     (b)
RAM_ADDR<3>           2       0     0   3     FB2_15  11    I/O     O
address<11>           2       0     0   3     FB2_16  10    I/O     I
RAM_ADDR<4>           2       0     0   3     FB2_17  12    I/O     O
address<10>           2       0     0   3     FB2_18  92    I/O     (b)

Signals Used by Logic in Function Block
  1: RAM_ADDR_0.LFBK    8: address<0>        15: address<5>.LFBK 
  2: RAM_ADDR_1.LFBK    9: address<10>.LFBK  16: address<6>.LFBK 
  3: RAM_ADDR_10.LFBK  10: address<11>.LFBK  17: address<7>.LFBK 
  4: RAM_ADDR_11.LFBK  11: address<1>        18: address<8>.LFBK 
  5: RAM_ADDR_2.LFBK   12: address<2>        19: address<9>.LFBK 
  6: RAM_ADDR_3.LFBK   13: address<3>.LFBK   20: clear 
  7: RAM_ADDR_4.LFBK   14: address<4>.LFBK   21: countUP 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
RAM_ADDR<0>          X......X...........X.................... 3       3
RAM_ADDR<1>          .X........X........X.................... 3       3
address<9>           .......X..XXXXXXXXXXX................... 12      12
RAM_ADDR<10>         ..X.....X..........X.................... 3       3
address<8>           .......X..XXXXXXXX.XX................... 11      11
RAM_ADDR<11>         ...X.....X.........X.................... 3       3
address<7>           .......X..XXXXXXX..XX................... 10      10
address<6>           .......X..XXXXXX...XX................... 9       9
address<5>           .......X..XXXXX....XX................... 8       8
RAM_ADDR<2>          ....X......X.......X.................... 3       3
address<4>           .......X..XXXX.....XX................... 7       7
address<3>           .......X..XXX......XX................... 6       6
RAM_ADDR<3>          .....X......X......X.................... 3       3
address<11>          .......XXXXXXXXXXXXXX................... 14      14
RAM_ADDR<4>          ......X......X.....X.................... 3       3
address<10>          .......XX.XXXXXXXXXXX................... 13      13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               18/18
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1   41    I/O     
RAM_ADDR<5>           2       0     0   3     FB3_2   32    I/O     O
(unused)              0       0     0   5     FB3_3   49    I/O     
RAM_ADDR<6>           2       0     0   3     FB3_4   50    I/O     O
(unused)              0       0     0   5     FB3_5   35    I/O     I
(unused)              0       0     0   5     FB3_6   53    I/O     
RAM_ADDR<7>           2       0     0   3     FB3_7   54    I/O     O
(unused)              0       0     0   5     FB3_8   37    I/O     I
(unused)              0       0     0   5     FB3_9   42    I/O     I
RAM_ADDR<8>           2       0     0   3     FB3_10  60    I/O     O
(unused)              0       0     0   5     FB3_11  52    I/O     I
(unused)              0       0     0   5     FB3_12  61    I/O     I
RAM_ADDR<9>           2       0     0   3     FB3_13  63    I/O     O
address<2>            2       0     0   3     FB3_14  55    I/O     I
address<1>            2       0     0   3     FB3_15  56    I/O     I
RAM_DATA<0>           2       0     0   3     FB3_16  65    I/O     O
address<0>            2       0     0   3     FB3_17  58    I/O     I
RAM_DATA<1>           2       0     0   3     FB3_18  59    I/O     O

Signals Used by Logic in Function Block
  1: RAM_ADDR_5.LFBK    7: address<1>.LFBK   13: address<9> 
  2: RAM_ADDR_6.LFBK    8: address<2>.LFBK   14: clear 
  3: RAM_ADDR_7.LFBK    9: address<5>        15: countUP 
  4: RAM_ADDR_8.LFBK   10: address<6>        16: in_data<0> 
  5: RAM_ADDR_9.LFBK   11: address<7>        17: in_data<1> 
  6: address<0>.LFBK   12: address<8>        18: in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
RAM_ADDR<5>          X.......X....X.......................... 3       3
RAM_ADDR<6>          .X.......X...X.......................... 3       3
RAM_ADDR<7>          ..X.......X..X.......................... 3       3
RAM_ADDR<8>          ...X.......X.X.......................... 3       3
RAM_ADDR<9>          ....X.......XX.......................... 3       3
address<2>           .....XXX.....XX......................... 5       5
address<1>           .....XX......XX......................... 4       4
RAM_DATA<0>          ...............X.X...................... 2       2
address<0>           .....X.......XX......................... 3       3
RAM_DATA<1>          ................XX...................... 2       2
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1   66    I/O     
(unused)              0       0     0   5     FB4_2   64    I/O     I
(unused)              0       0   \/5   0     FB4_3   71    I/O     (b)
(unused)              0       0   \/5   0     FB4_4   72    I/O     I
TRIGGER_N            25      20<-   0   0     FB4_5   67    I/O     O
(unused)              0       0   /\5   0     FB4_6   76    I/O     I
(unused)              0       0   /\5   0     FB4_7   77    I/O     I
(unused)              0       0     0   5     FB4_8   68    I/O     I
(unused)              0       0     0   5     FB4_9   70    I/O     I
(unused)              0       0     0   5     FB4_10  81    I/O     I
(unused)              0       0     0   5     FB4_11  74    I/O     I
(unused)              0       0     0   5     FB4_12  82    I/O     
(unused)              0       0     0   5     FB4_13  85    I/O     
(unused)              0       0     0   5     FB4_14  78    I/O     I
in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT
                      1       0     0   4     FB4_15  89    I/O     I
divider<0>            3       0     0   2     FB4_16  86    I/O     (b)
countUP               3       0     0   2     FB4_17  90    I/O     I
divider<1>            4       0     0   1     FB4_18  79    I/O     (b)

Signals Used by Logic in Function Block
  1: buffer_off        12: in_data<5>        22: trigger_data<6> 
  2: clear             13: in_data<6>        23: trigger_data<7> 
  3: clk_div<0>        14: in_data<7>        24: trigger_mask<0> 
  4: clk_div<1>        15: ram_read          25: trigger_mask<1> 
  5: divider<0>.LFBK   16: trigger_data<0>   26: trigger_mask<2> 
  6: divider<1>.LFBK   17: trigger_data<1>   27: trigger_mask<3> 
  7: in_data<0>        18: trigger_data<2>   28: trigger_mask<4> 
  8: in_data<1>        19: trigger_data<3>   29: trigger_mask<5> 
  9: in_data<2>        20: trigger_data<4>   30: trigger_mask<6> 
 10: in_data<3>        21: trigger_data<5>   31: trigger_mask<7> 
 11: in_data<4>       

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
TRIGGER_N            ......XXXXXXXXXXXXXXXXXXXXXXXXX......... 25      25
in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT 
                     X.............X......................... 2       2
divider<0>           .XXXX................................... 4       4
countUP              .XXXXX.................................. 5       5
divider<1>           .XXXXX.................................. 5       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********









FDCPE_RAM_ADDR0: FDCPE port map (RAM_ADDR(0),RAM_ADDR_D(0),clk_80,'0','0');
RAM_ADDR_D(0) <= ((clear AND RAM_ADDR_0.LFBK)
	OR (NOT clear AND address(0)));

FDCPE_RAM_ADDR1: FDCPE port map (RAM_ADDR(1),RAM_ADDR_D(1),clk_80,'0','0');
RAM_ADDR_D(1) <= ((clear AND RAM_ADDR_1.LFBK)
	OR (NOT clear AND address(1)));

FDCPE_RAM_ADDR2: FDCPE port map (RAM_ADDR(2),RAM_ADDR_D(2),clk_80,'0','0');
RAM_ADDR_D(2) <= ((clear AND RAM_ADDR_2.LFBK)
	OR (NOT clear AND address(2)));

FDCPE_RAM_ADDR3: FDCPE port map (RAM_ADDR(3),RAM_ADDR_D(3),clk_80,'0','0');
RAM_ADDR_D(3) <= ((clear AND RAM_ADDR_3.LFBK)
	OR (NOT clear AND address(3).LFBK));

FDCPE_RAM_ADDR4: FDCPE port map (RAM_ADDR(4),RAM_ADDR_D(4),clk_80,'0','0');
RAM_ADDR_D(4) <= ((clear AND RAM_ADDR_4.LFBK)
	OR (NOT clear AND address(4).LFBK));

FDCPE_RAM_ADDR5: FDCPE port map (RAM_ADDR(5),RAM_ADDR_D(5),clk_80,'0','0');
RAM_ADDR_D(5) <= ((clear AND RAM_ADDR_5.LFBK)
	OR (NOT clear AND address(5)));

FDCPE_RAM_ADDR6: FDCPE port map (RAM_ADDR(6),RAM_ADDR_D(6),clk_80,'0','0');
RAM_ADDR_D(6) <= ((clear AND RAM_ADDR_6.LFBK)
	OR (NOT clear AND address(6)));

FDCPE_RAM_ADDR7: FDCPE port map (RAM_ADDR(7),RAM_ADDR_D(7),clk_80,'0','0');
RAM_ADDR_D(7) <= ((clear AND RAM_ADDR_7.LFBK)
	OR (NOT clear AND address(7)));

FDCPE_RAM_ADDR8: FDCPE port map (RAM_ADDR(8),RAM_ADDR_D(8),clk_80,'0','0');
RAM_ADDR_D(8) <= ((clear AND RAM_ADDR_8.LFBK)
	OR (NOT clear AND address(8)));

FDCPE_RAM_ADDR9: FDCPE port map (RAM_ADDR(9),RAM_ADDR_D(9),clk_80,'0','0');
RAM_ADDR_D(9) <= ((clear AND RAM_ADDR_9.LFBK)
	OR (NOT clear AND address(9)));

FDCPE_RAM_ADDR10: FDCPE port map (RAM_ADDR(10),RAM_ADDR_D(10),clk_80,'0','0');
RAM_ADDR_D(10) <= ((clear AND RAM_ADDR_10.LFBK)
	OR (NOT clear AND address(10).LFBK));

FDCPE_RAM_ADDR11: FDCPE port map (RAM_ADDR(11),RAM_ADDR_D(11),clk_80,'0','0');
RAM_ADDR_D(11) <= ((clear AND RAM_ADDR_11.LFBK)
	OR (NOT clear AND address(11).LFBK));


RAM_DATA_I(0) <= in_data(0);
RAM_DATA(0) <= RAM_DATA_I(0) when RAM_DATA_OE(0) = '1' else 'Z';
RAM_DATA_OE(0) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT;


RAM_DATA_I(1) <= in_data(1);
RAM_DATA(1) <= RAM_DATA_I(1) when RAM_DATA_OE(1) = '1' else 'Z';
RAM_DATA_OE(1) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT;


RAM_DATA_I(2) <= in_data(2);
RAM_DATA(2) <= RAM_DATA_I(2) when RAM_DATA_OE(2) = '1' else 'Z';
RAM_DATA_OE(2) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT;


RAM_DATA_I(3) <= in_data(3);
RAM_DATA(3) <= RAM_DATA_I(3) when RAM_DATA_OE(3) = '1' else 'Z';
RAM_DATA_OE(3) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT;


RAM_DATA_I(4) <= in_data(4);
RAM_DATA(4) <= RAM_DATA_I(4) when RAM_DATA_OE(4) = '1' else 'Z';
RAM_DATA_OE(4) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT;


RAM_DATA_I(5) <= in_data(5);
RAM_DATA(5) <= RAM_DATA_I(5) when RAM_DATA_OE(5) = '1' else 'Z';
RAM_DATA_OE(5) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT;


RAM_DATA_I(6) <= in_data(6);
RAM_DATA(6) <= RAM_DATA_I(6) when RAM_DATA_OE(6) = '1' else 'Z';
RAM_DATA_OE(6) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT;


RAM_DATA_I(7) <= in_data(7);
RAM_DATA(7) <= RAM_DATA_I(7) when RAM_DATA_OE(7) = '1' else 'Z';
RAM_DATA_OE(7) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT;

FDCPE_RAM_OE: FDCPE port map (RAM_OE,NOT ram_read,clk_80,'0','0');

FDCPE_RAM_WE: FDCPE port map (RAM_WE,RAM_WE_D,clk_80,'0','0');
RAM_WE_D <= (countUP AND NOT ram_read);


TRIGGER_N <= ((ram_read)
	OR (EXP1_.EXP)
	OR (EXP2_.EXP)
	OR (in_data(6) AND NOT trigger_data(6))
	OR (in_data(7) AND NOT trigger_data(7))
	OR (trigger_mask(6) AND NOT trigger_data(6))
	OR (trigger_mask(7) AND NOT trigger_data(7)));

FDCPE_address0: FDCPE port map (address(0),address_D(0),clk_80,'0','0');
address_D(0) <= ((NOT clear AND countUP AND NOT address(0).LFBK)
	OR (NOT clear AND NOT countUP AND address(0).LFBK));

FTCPE_address1: FTCPE port map (address(1),address_T(1),clk_80,'0','0');
address_T(1) <= ((clear AND address(1).LFBK)
	OR (NOT clear AND countUP AND address(0).LFBK));

FTCPE_address2: FTCPE port map (address(2),address_T(2),clk_80,'0','0');
address_T(2) <= ((clear AND address(2).LFBK)
	OR (NOT clear AND countUP AND address(0).LFBK AND 
	address(1).LFBK));

FTCPE_address3: FTCPE port map (address(3),address_T(3),clk_80,'0','0');
address_T(3) <= ((clear AND address(3).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2)));

FTCPE_address4: FTCPE port map (address(4),address_T(4),clk_80,'0','0');
address_T(4) <= ((clear AND address(4).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2) AND address(3).LFBK));

FTCPE_address5: FTCPE port map (address(5),address_T(5),clk_80,'0','0');
address_T(5) <= ((clear AND address(5).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2) AND address(3).LFBK AND address(4).LFBK));

FTCPE_address6: FTCPE port map (address(6),address_T(6),clk_80,'0','0');
address_T(6) <= ((clear AND address(6).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2) AND address(3).LFBK AND address(4).LFBK AND 
	address(5).LFBK));

FTCPE_address7: FTCPE port map (address(7),address_T(7),clk_80,'0','0');
address_T(7) <= ((clear AND address(7).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2) AND address(3).LFBK AND address(4).LFBK AND 
	address(5).LFBK AND address(6).LFBK));

FTCPE_address8: FTCPE port map (address(8),address_T(8),clk_80,'0','0');
address_T(8) <= ((clear AND address(8).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2) AND address(3).LFBK AND address(4).LFBK AND 
	address(5).LFBK AND address(6).LFBK AND address(7).LFBK));

FTCPE_address9: FTCPE port map (address(9),address_T(9),clk_80,'0','0');
address_T(9) <= ((clear AND address(9).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2) AND address(3).LFBK AND address(4).LFBK AND 
	address(5).LFBK AND address(6).LFBK AND address(7).LFBK AND 
	address(8).LFBK));

FTCPE_address10: FTCPE port map (address(10),address_T(10),clk_80,'0','0');
address_T(10) <= ((clear AND address(10).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2) AND address(3).LFBK AND address(4).LFBK AND 
	address(5).LFBK AND address(6).LFBK AND address(7).LFBK AND 
	address(8).LFBK AND address(9).LFBK));

FTCPE_address11: FTCPE port map (address(11),address_T(11),clk_80,'0','0');
address_T(11) <= ((clear AND address(11).LFBK)
	OR (NOT clear AND countUP AND address(0) AND address(1) AND 
	address(2) AND address(10).LFBK AND address(3).LFBK AND 
	address(4).LFBK AND address(5).LFBK AND address(6).LFBK AND 
	address(7).LFBK AND address(8).LFBK AND address(9).LFBK));

FDCPE_countUP: FDCPE port map (countUP,countUP_D,clk_80,'0','0');
countUP_D <= ((clk_div(0) AND clk_div(1) AND NOT clear)
	OR (clk_div(0) AND NOT clear AND divider(0).LFBK AND 
	divider(1).LFBK)
	OR (clk_div(1) AND NOT clear AND divider(0).LFBK AND 
	NOT divider(1).LFBK));

FDCPE_divider0: FDCPE port map (divider(0),divider_D(0),clk_80,'0','0');
divider_D(0) <= ((clk_div(0) AND NOT clk_div(1) AND NOT clear AND 
	NOT divider(0).LFBK)
	OR (NOT clk_div(0) AND clk_div(1) AND NOT clear AND 
	NOT divider(0).LFBK)
	OR (NOT clk_div(0) AND NOT clk_div(1) AND NOT clear AND 
	divider(0).LFBK));

FDCPE_divider1: FDCPE port map (divider(1),divider_D(1),clk_80,'0','0');
divider_D(1) <= ((NOT clk_div(0) AND NOT clk_div(1) AND NOT clear AND 
	divider(1).LFBK)
	OR (NOT clk_div(0) AND NOT clear AND NOT divider(0).LFBK AND 
	divider(1).LFBK)
	OR (NOT clk_div(1) AND NOT clear AND NOT divider(0).LFBK AND 
	divider(1).LFBK)
	OR (clk_div(0) AND NOT clk_div(1) AND NOT clear AND 
	divider(0).LFBK AND NOT divider(1).LFBK));


in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT <= (NOT ram_read AND NOT buffer_off);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572-7-TQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13                XC9572-7-TQ100                63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 clk_div<1>                       51 VCC                           
  2 NC                               52 in_data<6>                    
  3 TIE                              53 TIE                           
  4 TIE                              54 RAM_ADDR<7>                   
  5 VCC                              55 ram_read                      
  6 RAM_ADDR<2>                      56 in_data<5>                    
  7 NC                               57 VCC                           
  8 TIE                              58 in_data<4>                    
  9 TIE                              59 RAM_DATA<1>                   
 10 trigger_mask<2>                  60 RAM_ADDR<8>                   
 11 RAM_ADDR<3>                      61 trigger_data<2>               
 12 RAM_ADDR<4>                      62 GND                           
 13 trigger_data<6>                  63 RAM_ADDR<9>                   
 14 RAM_DATA<2>                      64 in_data<0>                    
 15 trigger_data<3>                  65 RAM_DATA<0>                   
 16 RAM_DATA<4>                      66 TIE                           
 17 RAM_DATA<5>                      67 TRIGGER_N                     
 18 RAM_DATA<3>                      68 trigger_mask<5>               
 19 NC                               69 GND                           
 20 TIE                              70 trigger_mask<3>               
 21 GND                              71 TIE                           
 22 clk_80                           72 clear                         
 23 TIE                              73 NC                            
 24 NC                               74 trigger_data<0>               
 25 clk_div<0>                       75 GND                           
 26 VCC                              76 buffer_off                    
 27 TIE                              77 trigger_data<1>               
 28 RAM_DATA<6>                      78 trigger_data<7>               
 29 RAM_OE                           79 TIE                           
 30 trigger_data<4>                  80 NC                            
 31 GND                              81 in_data<3>                    
 32 RAM_ADDR<5>                      82 TIE                           
 33 trigger_mask<1>                  83 TDO                           
 34 NC                               84 GND                           
 35 trigger_mask<7>                  85 TIE                           
 36 RAM_DATA<7>                      86 TIE                           
 37 in_data<1>                       87 RAM_ADDR<0>                   
 38 VCC                              88 VCC                           
 39 RAM_WE                           89 in_data<7>                    
 40 TIE                              90 trigger_data<5>               
 41 TIE                              91 in_data<2>                    
 42 trigger_mask<6>                  92 TIE                           
 43 NC                               93 RAM_ADDR<1>                   
 44 GND                              94 trigger_mask<4>               
 45 TDI                              95 trigger_mask<0>               
 46 NC                               96 RAM_ADDR<10>                  
 47 TMS                              97 RAM_ADDR<11>                  
 48 TCK                              98 VCC                           
 49 TIE                              99 TIE                           
 50 RAM_ADDR<6>                     100 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572-7-TQ100
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25