Timing Report

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Design Name minilog
Device, Speed (SpeedFile Version) XC9572, -7 (3.0)
Date Created Wed Jul 08 10:39:46 2009
Created By Timing Report Generator: version J.33
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 12.000 ns.
Max. Clock Frequency (fSYSTEM) 83.333 MHz.
Limited by Cycle Time for clk_80
Clock to Setup (tCYC) 12.000 ns.
Pad to Pad Delay (tPD) 20.000 ns.
Setup to Clock at the Pad (tSU) 4.500 ns.
Clock Pad to Output Pad Delay (tCO) 4.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 12.0 120 120
AUTO_TS_P2P 0.0 20.0 63 63
AUTO_TS_P2F 0.0 6.0 36 36
AUTO_TS_F2P 0.0 3.0 14 14


Constraint: TS1000

Description: PERIOD:PERIOD_clk_80:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
address<0>.Q to RAM_ADDR<0>.D 0.000 12.000 -12.000
address<0>.Q to address<10>.D 0.000 12.000 -12.000
address<0>.Q to address<11>.D 0.000 12.000 -12.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
buffer_off to RAM_DATA<0> 0.000 20.000 -20.000
buffer_off to RAM_DATA<1> 0.000 20.000 -20.000
buffer_off to RAM_DATA<2> 0.000 20.000 -20.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
clear to RAM_ADDR<0>.D 0.000 6.000 -6.000
clear to RAM_ADDR<10>.D 0.000 6.000 -6.000
clear to RAM_ADDR<11>.D 0.000 6.000 -6.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
RAM_ADDR<0>.Q to RAM_ADDR<0> 0.000 3.000 -3.000
RAM_ADDR<10>.Q to RAM_ADDR<10> 0.000 3.000 -3.000
RAM_ADDR<11>.Q to RAM_ADDR<11> 0.000 3.000 -3.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
clk_80 83.333 Limited by Cycle Time for clk_80

Setup/Hold Times for Clocks

Setup/Hold Times for Clock clk_80
Source Pad Setup to clk (edge) Hold to clk (edge)
clear 4.500 0.000
clk_div<0> 4.500 0.000
clk_div<1> 4.500 0.000
ram_read 4.500 0.000


Clock to Pad Timing

Clock clk_80 to Pad
Destination Pad Clock (edge) to Pad
RAM_ADDR<0> 4.500
RAM_ADDR<10> 4.500
RAM_ADDR<11> 4.500
RAM_ADDR<1> 4.500
RAM_ADDR<2> 4.500
RAM_ADDR<3> 4.500
RAM_ADDR<4> 4.500
RAM_ADDR<5> 4.500
RAM_ADDR<6> 4.500
RAM_ADDR<7> 4.500
RAM_ADDR<8> 4.500
RAM_ADDR<9> 4.500
RAM_OE 4.500
RAM_WE 4.500


Clock to Setup Times for Clocks

Clock to Setup for clock clk_80
Source Destination Delay
address<0>.Q RAM_ADDR<0>.D 12.000
address<0>.Q address<10>.D 12.000
address<0>.Q address<11>.D 12.000
address<0>.Q address<3>.D 12.000
address<0>.Q address<4>.D 12.000
address<0>.Q address<5>.D 12.000
address<0>.Q address<6>.D 12.000
address<0>.Q address<7>.D 12.000
address<0>.Q address<8>.D 12.000
address<0>.Q address<9>.D 12.000
address<1>.Q RAM_ADDR<1>.D 12.000
address<1>.Q address<10>.D 12.000
address<1>.Q address<11>.D 12.000
address<1>.Q address<3>.D 12.000
address<1>.Q address<4>.D 12.000
address<1>.Q address<5>.D 12.000
address<1>.Q address<6>.D 12.000
address<1>.Q address<7>.D 12.000
address<1>.Q address<8>.D 12.000
address<1>.Q address<9>.D 12.000
address<2>.Q RAM_ADDR<2>.D 12.000
address<2>.Q address<10>.D 12.000
address<2>.Q address<11>.D 12.000
address<2>.Q address<3>.D 12.000
address<2>.Q address<4>.D 12.000
address<2>.Q address<5>.D 12.000
address<2>.Q address<6>.D 12.000
address<2>.Q address<7>.D 12.000
address<2>.Q address<8>.D 12.000
address<2>.Q address<9>.D 12.000
address<5>.Q RAM_ADDR<5>.D 12.000
address<6>.Q RAM_ADDR<6>.D 12.000
address<7>.Q RAM_ADDR<7>.D 12.000
address<8>.Q RAM_ADDR<8>.D 12.000
address<9>.Q RAM_ADDR<9>.D 12.000
countUP.Q RAM_WE.D 12.000
countUP.Q address<0>.D 12.000
countUP.Q address<10>.D 12.000
countUP.Q address<11>.D 12.000
countUP.Q address<1>.D 12.000
countUP.Q address<2>.D 12.000
countUP.Q address<3>.D 12.000
countUP.Q address<4>.D 12.000
countUP.Q address<5>.D 12.000
countUP.Q address<6>.D 12.000
countUP.Q address<7>.D 12.000
countUP.Q address<8>.D 12.000
countUP.Q address<9>.D 12.000
RAM_ADDR<0>.Q RAM_ADDR<0>.D 8.000
RAM_ADDR<10>.Q RAM_ADDR<10>.D 8.000
RAM_ADDR<11>.Q RAM_ADDR<11>.D 8.000
RAM_ADDR<1>.Q RAM_ADDR<1>.D 8.000
RAM_ADDR<2>.Q RAM_ADDR<2>.D 8.000
RAM_ADDR<3>.Q RAM_ADDR<3>.D 8.000
RAM_ADDR<4>.Q RAM_ADDR<4>.D 8.000
RAM_ADDR<5>.Q RAM_ADDR<5>.D 8.000
RAM_ADDR<6>.Q RAM_ADDR<6>.D 8.000
RAM_ADDR<7>.Q RAM_ADDR<7>.D 8.000
RAM_ADDR<8>.Q RAM_ADDR<8>.D 8.000
RAM_ADDR<9>.Q RAM_ADDR<9>.D 8.000
address<0>.Q address<0>.D 8.000
address<0>.Q address<1>.D 8.000
address<0>.Q address<2>.D 8.000
address<10>.Q RAM_ADDR<10>.D 8.000
address<10>.Q address<10>.D 8.000
address<10>.Q address<11>.D 8.000
address<11>.Q RAM_ADDR<11>.D 8.000
address<11>.Q address<11>.D 8.000
address<1>.Q address<1>.D 8.000
address<1>.Q address<2>.D 8.000
address<2>.Q address<2>.D 8.000
address<3>.Q RAM_ADDR<3>.D 8.000
address<3>.Q address<10>.D 8.000
address<3>.Q address<11>.D 8.000
address<3>.Q address<3>.D 8.000
address<3>.Q address<4>.D 8.000
address<3>.Q address<5>.D 8.000
address<3>.Q address<6>.D 8.000
address<3>.Q address<7>.D 8.000
address<3>.Q address<8>.D 8.000
address<3>.Q address<9>.D 8.000
address<4>.Q RAM_ADDR<4>.D 8.000
address<4>.Q address<10>.D 8.000
address<4>.Q address<11>.D 8.000
address<4>.Q address<4>.D 8.000
address<4>.Q address<5>.D 8.000
address<4>.Q address<6>.D 8.000
address<4>.Q address<7>.D 8.000
address<4>.Q address<8>.D 8.000
address<4>.Q address<9>.D 8.000
address<5>.Q address<10>.D 8.000
address<5>.Q address<11>.D 8.000
address<5>.Q address<5>.D 8.000
address<5>.Q address<6>.D 8.000
address<5>.Q address<7>.D 8.000
address<5>.Q address<8>.D 8.000
address<5>.Q address<9>.D 8.000
address<6>.Q address<10>.D 8.000
address<6>.Q address<11>.D 8.000
address<6>.Q address<6>.D 8.000
address<6>.Q address<7>.D 8.000
address<6>.Q address<8>.D 8.000
address<6>.Q address<9>.D 8.000
address<7>.Q address<10>.D 8.000
address<7>.Q address<11>.D 8.000
address<7>.Q address<7>.D 8.000
address<7>.Q address<8>.D 8.000
address<7>.Q address<9>.D 8.000
address<8>.Q address<10>.D 8.000
address<8>.Q address<11>.D 8.000
address<8>.Q address<8>.D 8.000
address<8>.Q address<9>.D 8.000
address<9>.Q address<10>.D 8.000
address<9>.Q address<11>.D 8.000
address<9>.Q address<9>.D 8.000
divider<0>.Q countUP.D 8.000
divider<0>.Q divider<0>.D 8.000
divider<0>.Q divider<1>.D 8.000
divider<1>.Q countUP.D 8.000
divider<1>.Q divider<1>.D 8.000


Pad to Pad List

Source Pad Destination Pad Delay
buffer_off RAM_DATA<0> 20.000
buffer_off RAM_DATA<1> 20.000
buffer_off RAM_DATA<2> 20.000
buffer_off RAM_DATA<3> 20.000
buffer_off RAM_DATA<4> 20.000
buffer_off RAM_DATA<5> 20.000
buffer_off RAM_DATA<6> 20.000
buffer_off RAM_DATA<7> 20.000
ram_read RAM_DATA<0> 20.000
ram_read RAM_DATA<1> 20.000
ram_read RAM_DATA<2> 20.000
ram_read RAM_DATA<3> 20.000
ram_read RAM_DATA<4> 20.000
ram_read RAM_DATA<5> 20.000
ram_read RAM_DATA<6> 20.000
ram_read RAM_DATA<7> 20.000
in_data<0> TRIGGER_N 9.500
in_data<1> TRIGGER_N 9.500
in_data<2> TRIGGER_N 9.500
in_data<3> TRIGGER_N 9.500
in_data<4> TRIGGER_N 9.500
in_data<5> TRIGGER_N 9.500
in_data<6> TRIGGER_N 9.500
in_data<7> TRIGGER_N 9.500
trigger_data<0> TRIGGER_N 9.500
trigger_data<1> TRIGGER_N 9.500
trigger_data<2> TRIGGER_N 9.500
trigger_data<3> TRIGGER_N 9.500
trigger_data<4> TRIGGER_N 9.500
trigger_data<5> TRIGGER_N 9.500
trigger_data<6> TRIGGER_N 9.500
trigger_data<7> TRIGGER_N 9.500
trigger_mask<0> TRIGGER_N 9.500
trigger_mask<1> TRIGGER_N 9.500
trigger_mask<2> TRIGGER_N 9.500
trigger_mask<3> TRIGGER_N 9.500
trigger_mask<4> TRIGGER_N 9.500
trigger_mask<5> TRIGGER_N 9.500
trigger_mask<6> TRIGGER_N 9.500
trigger_mask<7> TRIGGER_N 9.500
in_data<0> RAM_DATA<0> 7.500
in_data<1> RAM_DATA<1> 7.500
in_data<2> RAM_DATA<2> 7.500
in_data<3> RAM_DATA<3> 7.500
in_data<4> RAM_DATA<4> 7.500
in_data<5> RAM_DATA<5> 7.500
in_data<6> RAM_DATA<6> 7.500
in_data<7> RAM_DATA<7> 7.500
ram_read TRIGGER_N 7.500



Number of paths analyzed: 233
Number of Timing errors: 233
Analysis Completed: Wed Jul 08 10:39:46 2009