********** Mapped Logic ********** |
FDCPE_RAM_ADDR0: FDCPE port map (RAM_ADDR(0),RAM_ADDR_D(0),clk_80,'0','0');
RAM_ADDR_D(0) <= ((clear AND RAM_ADDR_0.LFBK) OR (NOT clear AND address(0))); |
FDCPE_RAM_ADDR1: FDCPE port map (RAM_ADDR(1),RAM_ADDR_D(1),clk_80,'0','0');
RAM_ADDR_D(1) <= ((clear AND RAM_ADDR_1.LFBK) OR (NOT clear AND address(1))); |
FDCPE_RAM_ADDR2: FDCPE port map (RAM_ADDR(2),RAM_ADDR_D(2),clk_80,'0','0');
RAM_ADDR_D(2) <= ((clear AND RAM_ADDR_2.LFBK) OR (NOT clear AND address(2))); |
FDCPE_RAM_ADDR3: FDCPE port map (RAM_ADDR(3),RAM_ADDR_D(3),clk_80,'0','0');
RAM_ADDR_D(3) <= ((clear AND RAM_ADDR_3.LFBK) OR (NOT clear AND address(3).LFBK)); |
FDCPE_RAM_ADDR4: FDCPE port map (RAM_ADDR(4),RAM_ADDR_D(4),clk_80,'0','0');
RAM_ADDR_D(4) <= ((clear AND RAM_ADDR_4.LFBK) OR (NOT clear AND address(4).LFBK)); |
FDCPE_RAM_ADDR5: FDCPE port map (RAM_ADDR(5),RAM_ADDR_D(5),clk_80,'0','0');
RAM_ADDR_D(5) <= ((clear AND RAM_ADDR_5.LFBK) OR (NOT clear AND address(5))); |
FDCPE_RAM_ADDR6: FDCPE port map (RAM_ADDR(6),RAM_ADDR_D(6),clk_80,'0','0');
RAM_ADDR_D(6) <= ((clear AND RAM_ADDR_6.LFBK) OR (NOT clear AND address(6))); |
FDCPE_RAM_ADDR7: FDCPE port map (RAM_ADDR(7),RAM_ADDR_D(7),clk_80,'0','0');
RAM_ADDR_D(7) <= ((clear AND RAM_ADDR_7.LFBK) OR (NOT clear AND address(7))); |
FDCPE_RAM_ADDR8: FDCPE port map (RAM_ADDR(8),RAM_ADDR_D(8),clk_80,'0','0');
RAM_ADDR_D(8) <= ((clear AND RAM_ADDR_8.LFBK) OR (NOT clear AND address(8))); |
FDCPE_RAM_ADDR9: FDCPE port map (RAM_ADDR(9),RAM_ADDR_D(9),clk_80,'0','0');
RAM_ADDR_D(9) <= ((clear AND RAM_ADDR_9.LFBK) OR (NOT clear AND address(9))); |
FDCPE_RAM_ADDR10: FDCPE port map (RAM_ADDR(10),RAM_ADDR_D(10),clk_80,'0','0');
RAM_ADDR_D(10) <= ((clear AND RAM_ADDR_10.LFBK) OR (NOT clear AND address(10).LFBK)); |
FDCPE_RAM_ADDR11: FDCPE port map (RAM_ADDR(11),RAM_ADDR_D(11),clk_80,'0','0');
RAM_ADDR_D(11) <= ((clear AND RAM_ADDR_11.LFBK) OR (NOT clear AND address(11).LFBK)); |
RAM_DATA_I(0) <= in_data(0);
RAM_DATA(0) <= RAM_DATA_I(0) when RAM_DATA_OE(0) = '1' else 'Z'; RAM_DATA_OE(0) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT; |
RAM_DATA_I(1) <= in_data(1);
RAM_DATA(1) <= RAM_DATA_I(1) when RAM_DATA_OE(1) = '1' else 'Z'; RAM_DATA_OE(1) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT; |
RAM_DATA_I(2) <= in_data(2);
RAM_DATA(2) <= RAM_DATA_I(2) when RAM_DATA_OE(2) = '1' else 'Z'; RAM_DATA_OE(2) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT; |
RAM_DATA_I(3) <= in_data(3);
RAM_DATA(3) <= RAM_DATA_I(3) when RAM_DATA_OE(3) = '1' else 'Z'; RAM_DATA_OE(3) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT; |
RAM_DATA_I(4) <= in_data(4);
RAM_DATA(4) <= RAM_DATA_I(4) when RAM_DATA_OE(4) = '1' else 'Z'; RAM_DATA_OE(4) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT; |
RAM_DATA_I(5) <= in_data(5);
RAM_DATA(5) <= RAM_DATA_I(5) when RAM_DATA_OE(5) = '1' else 'Z'; RAM_DATA_OE(5) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT; |
RAM_DATA_I(6) <= in_data(6);
RAM_DATA(6) <= RAM_DATA_I(6) when RAM_DATA_OE(6) = '1' else 'Z'; RAM_DATA_OE(6) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT; |
RAM_DATA_I(7) <= in_data(7);
RAM_DATA(7) <= RAM_DATA_I(7) when RAM_DATA_OE(7) = '1' else 'Z'; RAM_DATA_OE(7) <= NOT in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT; |
FDCPE_RAM_OE: FDCPE port map (RAM_OE,NOT ram_read,clk_80,'0','0'); |
FDCPE_RAM_WE: FDCPE port map (RAM_WE,RAM_WE_D,clk_80,'0','0');
RAM_WE_D <= (countUP AND NOT ram_read); |
TRIGGER_N <= ((ram_read)
OR (EXP1_.EXP) OR (EXP2_.EXP) OR (in_data(6) AND NOT trigger_data(6)) OR (in_data(7) AND NOT trigger_data(7)) OR (trigger_mask(6) AND NOT trigger_data(6)) OR (trigger_mask(7) AND NOT trigger_data(7))); |
FDCPE_address0: FDCPE port map (address(0),address_D(0),clk_80,'0','0');
address_D(0) <= ((NOT clear AND countUP AND NOT address(0).LFBK) OR (NOT clear AND NOT countUP AND address(0).LFBK)); |
FTCPE_address1: FTCPE port map (address(1),address_T(1),clk_80,'0','0');
address_T(1) <= ((clear AND address(1).LFBK) OR (NOT clear AND countUP AND address(0).LFBK)); |
FTCPE_address2: FTCPE port map (address(2),address_T(2),clk_80,'0','0');
address_T(2) <= ((clear AND address(2).LFBK) OR (NOT clear AND countUP AND address(0).LFBK AND address(1).LFBK)); |
FTCPE_address3: FTCPE port map (address(3),address_T(3),clk_80,'0','0');
address_T(3) <= ((clear AND address(3).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2))); |
FTCPE_address4: FTCPE port map (address(4),address_T(4),clk_80,'0','0');
address_T(4) <= ((clear AND address(4).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2) AND address(3).LFBK)); |
FTCPE_address5: FTCPE port map (address(5),address_T(5),clk_80,'0','0');
address_T(5) <= ((clear AND address(5).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2) AND address(3).LFBK AND address(4).LFBK)); |
FTCPE_address6: FTCPE port map (address(6),address_T(6),clk_80,'0','0');
address_T(6) <= ((clear AND address(6).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2) AND address(3).LFBK AND address(4).LFBK AND address(5).LFBK)); |
FTCPE_address7: FTCPE port map (address(7),address_T(7),clk_80,'0','0');
address_T(7) <= ((clear AND address(7).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2) AND address(3).LFBK AND address(4).LFBK AND address(5).LFBK AND address(6).LFBK)); |
FTCPE_address8: FTCPE port map (address(8),address_T(8),clk_80,'0','0');
address_T(8) <= ((clear AND address(8).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2) AND address(3).LFBK AND address(4).LFBK AND address(5).LFBK AND address(6).LFBK AND address(7).LFBK)); |
FTCPE_address9: FTCPE port map (address(9),address_T(9),clk_80,'0','0');
address_T(9) <= ((clear AND address(9).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2) AND address(3).LFBK AND address(4).LFBK AND address(5).LFBK AND address(6).LFBK AND address(7).LFBK AND address(8).LFBK)); |
FTCPE_address10: FTCPE port map (address(10),address_T(10),clk_80,'0','0');
address_T(10) <= ((clear AND address(10).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2) AND address(3).LFBK AND address(4).LFBK AND address(5).LFBK AND address(6).LFBK AND address(7).LFBK AND address(8).LFBK AND address(9).LFBK)); |
FTCPE_address11: FTCPE port map (address(11),address_T(11),clk_80,'0','0');
address_T(11) <= ((clear AND address(11).LFBK) OR (NOT clear AND countUP AND address(0) AND address(1) AND address(2) AND address(10).LFBK AND address(3).LFBK AND address(4).LFBK AND address(5).LFBK AND address(6).LFBK AND address(7).LFBK AND address(8).LFBK AND address(9).LFBK)); |
FDCPE_countUP: FDCPE port map (countUP,countUP_D,clk_80,'0','0');
countUP_D <= ((clk_div(0) AND clk_div(1) AND NOT clear) OR (clk_div(0) AND NOT clear AND divider(0).LFBK AND divider(1).LFBK) OR (clk_div(1) AND NOT clear AND divider(0).LFBK AND NOT divider(1).LFBK)); |
FDCPE_divider0: FDCPE port map (divider(0),divider_D(0),clk_80,'0','0');
divider_D(0) <= ((clk_div(0) AND NOT clk_div(1) AND NOT clear AND NOT divider(0).LFBK) OR (NOT clk_div(0) AND clk_div(1) AND NOT clear AND NOT divider(0).LFBK) OR (NOT clk_div(0) AND NOT clk_div(1) AND NOT clear AND divider(0).LFBK)); |
FDCPE_divider1: FDCPE port map (divider(1),divider_D(1),clk_80,'0','0');
divider_D(1) <= ((NOT clk_div(0) AND NOT clk_div(1) AND NOT clear AND divider(1).LFBK) OR (NOT clk_div(0) AND NOT clear AND NOT divider(0).LFBK AND divider(1).LFBK) OR (NOT clk_div(1) AND NOT clear AND NOT divider(0).LFBK AND divider(1).LFBK) OR (clk_div(0) AND NOT clk_div(1) AND NOT clear AND divider(0).LFBK AND NOT divider(1).LFBK)); |
in_data_7_IBUF$BUF0/in_data_7_IBUF$BUF0_TRST__$INT <= (NOT ram_read AND NOT buffer_off); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |