---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:32:39 07/10/2009 -- Design Name: -- Module Name: edge_det - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity edge_det is Port ( clk: in STD_LOGIC; reset : in STD_LOGIC; sync_out_h : out STD_LOGIC; sync_out_l : out STD_LOGIC; async : in STD_LOGIC ); end edge_det; architecture Behavioral of edge_det is signal async_tmp: std_logic_vector (2 downto 0); signal sync_h : STD_LOGIC; signal sync_l : STD_LOGIC; begin process (clk) is begin if rising_edge (CLK) then if reset = '1' then sync_h <= '0'; sync_l <= '0'; async_tmp <= "000"; else async_tmp <= async_tmp(1 downto 0) & async; case async_tmp(2 downto 1) is when "10" => sync_l <= '1'; --sync_h <= '0'; when "01" => sync_h <= '1'; --sync_l <= '0'; when others => sync_h <= '0'; sync_l <= '0'; end case; end if; end if; end process; sync_out_h <= sync_h; sync_out_l <= sync_l; end Behavioral;