-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:43:10 07/14/2009 -- Design Name: edge_det -- Module Name: C:/Programme/Xilinx92i/rle_encoder/test3_tb.vhd -- Project Name: rle_encoder -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: edge_det -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; use ieee.math_real.all; ENTITY test3_tb_vhd IS END test3_tb_vhd; ARCHITECTURE behavior OF test3_tb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT edge_det PORT( clk : IN std_logic; reset : IN std_logic; async : IN std_logic; sync_out_h : out STD_LOGIC; sync_out_l : out STD_LOGIC ); END COMPONENT; --Inputs SIGNAL clk : std_logic := '0'; SIGNAL reset : std_logic := '0'; SIGNAL async : std_logic := '0'; --Outputs SIGNAL sync_out_h : STD_LOGIC; SIGNAL sync_out_l : STD_LOGIC; BEGIN -- Instantiate the Unit Under Test (UUT) uut: edge_det PORT MAP( clk => clk, reset => reset, sync_out_h => sync_out_h, sync_out_l => sync_out_l, async => async ); clk_gen : process begin while now < 1000 ns loop clk <= not clk; wait for 5 ns; end loop; wait; end process; -- Produce a randomly-changing async signal. stim : process variable seed1, seed2 : POSITIVE; variable Rand : REAL; variable IRand : INTEGER; begin while now < 1000 ns loop wait until FALLING_EDGE(Clk); -- make a random real between 0 and 1 uniform(seed1, seed2, rand); -- turn it into a random integer between 50 and 150 irand := integer((rand * 100.0 - 0.5) + 50.0 ); -- wait for that many ns wait for irand * 1 ns; async <= not async; end loop; wait; end process; END;