library ieee;
use ieee.std_logic_1164.all;

entity tb_AD7960_conversion_freq is
end tb_AD7960_conversion_freq;

architecture tb of tb_AD7960_conversion_freq is

    component AD7960_conversion_freq
        port (DINp    : in std_logic;
              DCOp    : out std_logic;
              DCIp    : in std_logic;
              CNVp    : out std_logic;
              clk     : in std_logic;
              sync_clk : in std_logic;              
              aresetn : in std_logic;
              conv    : in std_logic;
              data    : out std_logic_vector (16-1 downto 0);
              dvalid  : out std_logic);
    end component;

    signal DINp    : std_logic;
    signal DCOp    : std_logic;
    signal DCIp    : std_logic;
    signal CNVp    : std_logic;
    signal clk     : std_logic;
    signal sync_clk : std_logic;
    signal aresetn : std_logic;
    signal conv    : std_logic;
    signal data    : std_logic_vector (16-1 downto 0);
    signal dvalid  : std_logic;

    constant TbPeriod : time := 10 ns; -- EDIT Put right period here
    constant CNVPeriod : time := 333 ns; -- EDIT Put right period here
    constant SYNCPeriod : time := 5 ns; -- EDIT Put right period here
    
    signal TbClock : std_logic := '0';
    signal TbSimEnded : std_logic := '0';
    signal ConvClock : std_logic := '0';
    signal SyncClock : std_logic := '0';

    procedure send_data( d  : std_logic_vector; -- data to send         
    -- Signal interface
    signal DC  : in  std_logic;
    signal Data : out std_logic ) is
        begin          
          for i in d'range loop        
            --wait for 18 ns;
            Data    <= d(i);
            wait until falling_edge(DC);    
          end loop;
          wait until rising_edge(DC);
    end procedure send_data;
    

begin
    



    dut : AD7960_conversion_freq
    port map (DINp    => DINp,
              DCOp    => DCOp,
              DCIp    => DCIp,
              CNVp    => CNVp,
              clk     => clk,
              sync_clk => sync_clk,              
              aresetn => aresetn,
              conv    => conv,
              data    => data,
              dvalid  => dvalid);

    -- Clock generation
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
    ConvClock <= not ConvClock after CNVPeriod/2 when TbSimEnded /= '1' else '0';
    SyncClock <=not SyncClock after SYNCPeriod/2 when TbSimEnded /= '1' else '0';

    -- EDIT: Check that clk is really your main clock signal
    clk <= TbClock;
    conv <= ConvClock;
    DCIp <= DCOp;-- after 3ns;
    sync_clk <= SyncClock;
    
    stimuli : process
    begin
        -- EDIT Adapt initialization as needed
        --DINp <= '0';
        --DCIp <= '0';
        --conv <= '0';

        -- Reset generation
        -- EDIT: Check that aresetn is really your reset signal
        aresetn <= '0';
        wait for 100 ns;
        aresetn <= '1';
        wait for 100 ns;
        --conv <= ConvClock;
        -- EDIT Add stimuli here
        --wait for 10 * TbPeriod;
        --DCIp <= DCOp;-- after 3ns;
        wait until rising_edge(DCOp);
        send_data(x"F3A0", DCOp, DINp);
         wait until rising_edge(DCOp);
        
        send_data(x"F3A0", DCOp, DINp); 
         wait until rising_edge(DCOp);
        
        send_data(x"1234", DCOp, DINp);
         wait until rising_edge(DCOp);
        
        send_data(x"F0F0", DCOp, DINp);

        wait for 100 ns;
        -- Stop the clock and hence terminate the simulation
        TbSimEnded <= '1';
        wait;
    end process;

end tb;

-- Configuration block below is required by some simulators. Usually no need to edit.

configuration cfg_tb_AD7960_conversion_freq of tb_AD7960_conversion_freq is
    for tb
    end for;
end cfg_tb_AD7960_conversion_freq;