library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;

entity AD7961_sim is
	port
	(
		CLKp                 : in    std_logic;
		CLKn                 : in    std_logic;
		CNVp                 : in    std_logic;
		CNVn                 : in    std_logic;
		DCOp                 : out   std_logic;
		DCOn                 : out   std_logic;
		Dp                   : out   std_logic;
		Dn                   : out   std_logic;
		EN                   : in    std_logic_vector(3 downto 0)
	);
end AD7961_sim;

architecture sim of AD7961_sim is

--- CLOCK ---
signal counter500            : integer range 0 to 99 := 0;
signal CLKp_buff             : std_logic := '0';
signal CNVp_buff             : std_logic := '0';
signal pause_counter         : unsigned(7 downto 0) := (others => '0');


--- DATA ---
type ROM512kx18 is array (0 to 511) of signed(15 downto 0); 
signal ROM                   : ROM512kx18;
signal counter               : unsigned(8 downto 0) := (others => '0');
signal samplecounter         : unsigned(8 downto 0) := (others => '0');
signal speed                 : unsigned(8 downto 0) := "000000001";

signal ADC_Data_buff         : std_logic_vector(15 downto 0) := (others => '0');
signal ADC_Data_SR           : std_logic_vector(15 downto 0) := (others => '0');

begin

DCOp                         <= transport CLKp after 3ns;
DCOn                         <= transport CLKn after 3ns;
Dp                           <= ADC_Data_SR(15);
Dn                           <= not ADC_Data_SR(15);

process begin
	wait for 2 ns;
	CLKp_buff                <= CLKp;
	CNVp_buff                <= CNVp;

	if CLKp_buff = '1' and CLKp = '0' then
		ADC_Data_SR          <= ADC_Data_SR(14 downto 0) & '0';
	end if;

	if CNVp_buff = '0' and CNVp = '1' then
		samplecounter        <= samplecounter + 1;
		counter              <= counter + speed;
		if samplecounter = 511 then
			speed            <= speed + 4;
			samplecounter    <= (others => '0');
		end if;
		if speed > 510 and samplecounter = 511 then
			wait;
		end if;
		ADC_Data_buff        <= std_logic_vector(ROM(to_integer(counter)));
	end if;

	pause_counter            <= pause_counter + 1;
	if CLKp = '1' then
		pause_counter        <= (others => '0');
	end if;
	if pause_counter = 10 then -- set new sample after 20 ns CLK pause
		ADC_Data_SR          <= ADC_Data_buff;
	end if;

end process;

tabel: for I in 0 to 511 generate
	ROM(I)                   <= to_signed(integer(sin(2.0*MATH_PI*(real(I)+0.5)/512.0)*32767.5),16);
end generate;

end;