library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

library work;

entity tb_AD7961 is
end tb_AD7961;

architecture tb of tb_AD7961 is

signal clk100                : std_logic := '0';
-- inside FPGA
signal data_ready            : std_logic := '0';
signal data                  : std_logic_vector(15 downto 0) := (others => '0');
-- ADC <-> FPGA
signal EN                    : std_logic_vector(3 downto 0) := (others => '0');
signal CLKp                  : std_logic := '0';
signal CLKn                  : std_logic := '0';
signal CNVp                  : std_logic := '0';
signal CNVn                  : std_logic := '0';
signal DCOp                  : std_logic := '0';
signal DCOn                  : std_logic := '0';
signal Dp                    : std_logic := '0';
signal Dn                    : std_logic := '0';


begin

clk100 <= not clk100 after 5 ns;

inst_AD7961 : entity work.AD7961
	port map
	(
		CLK100               => clk100,
		data_ready           => data_ready,
		data                 => data,
		EN                   => EN,
		CLKp                 => CLKp,
		CLKn                 => CLKn,
		CNVp                 => CNVp,
		CNVn                 => CNVn,
		DCOp                 => DCOp,
		DCOn                 => DCOn,
		Dp                   => Dp,
		Dn                   => Dn
	);

inst_AD7961_sim : entity work.AD7961_sim
	port map
	(
		CLKp                 => CLKp,
		CLKn                 => CLKn,
		CNVp                 => CNVp,
		CNVn                 => CNVn,
		DCOp                 => DCOp,
		DCOn                 => DCOn,
		Dp                   => Dp,
		Dn                   => Dn,
		EN                   => EN
	);

end;