library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

library UNISIM;
use UNISIM.Vcomponents.all;

entity AD7961 is
	port
	(
		CLK100               : in    std_logic;
		data_ready           : out   std_logic;
		data                 : out   std_logic_vector(15 downto 0);
		EN                   : out   std_logic_vector(3 downto 0);
		CLKp                 : out   std_logic;
		CLKn                 : out   std_logic;
		CNVp                 : out   std_logic;
		CNVn                 : out   std_logic;
		DCOp                 : in    std_logic;
		DCOn                 : in    std_logic;
		Dp                   : in    std_logic;
		Dn                   : in    std_logic
	);
end AD7961;

architecture rtl of AD7961 is

signal DCO                   : std_logic := '0';
signal D                     : std_logic := '0';
signal data_buffer           : std_logic_vector(15 downto 0) := (others => '0');
signal counter_100           : integer range 0 to 19 := 0;

signal CNV_data              : std_logic_vector(0 to 39) := "1110000000000000000000000000000000000000";
signal CNV_D_p               : std_logic := '0';
signal CNV_D_n               : std_logic := '0';
signal CNV                   : std_logic := '0';

signal CLK_data              : std_logic_vector(0 to 39) := "0101010101010101010101010101010100000000";
signal CLK_D_p               : std_logic := '0';
signal CLK_D_n               : std_logic := '0';
signal CLK                   : std_logic := '0';

begin

EN                           <= "1010"; -- Normal: 0010, TEST: 1100

IBUFDS_DCO: IBUFDS
	generic map
	(
		DIFF_TERM            => TRUE,
		IBUF_LOW_PWR         => FALSE,
		IOSTANDARD           => "LVDS_25"
	)
	port map
	(
		O                    => DCO,
		I                    => DCOp,
		IB                   => DCOn
	);

IBUFDS_D: IBUFDS
	generic map
	(
		DIFF_TERM            => TRUE,
		IBUF_LOW_PWR         => FALSE,
		IOSTANDARD           => "LVDS_25"
	)
	port map
	(
		O                    => D,
		I                    => Dp,
		IB                   => Dn
	);

inst_ODDR_CLK : ODDR
	generic map
	(
		DDR_CLK_EDGE         => "OPPOSITE_EDGE",
		INIT                 => '0',
		SRTYPE               => "SYNC"
	)
	port map
	(
		Q                    => CLK,
		C                    => CLK100,
		CE                   => '1',
		D1                   => CLK_D_p,
		D2                   => CLK_D_n,
		R                    => '0',
		S                    => '0'
	);

OBUFDS_CLK: OBUFDS
	generic map
	(
		IOSTANDARD           => "LVDS_25",
		SLEW                 => "FAST"
	)
	port map
	(
		O                    => CLKp, 
		OB                   => CLKn,
		I                    => CLK
	);

inst_ODDR_CNV : ODDR
	generic map
	(
		DDR_CLK_EDGE         => "OPPOSITE_EDGE",
		INIT                 => '0',
		SRTYPE               => "SYNC"
	)
	port map
	(
		Q                    => CNV,
		C                    => CLK100,
		CE                   => '1',
		D1                   => CNV_D_p,
		D2                   => CNV_D_n,
		R                    => '0',
		S                    => '0'
	);

OBUFDS_CNV: OBUFDS
	generic map
	(
		IOSTANDARD           => "LVDS_25",
		SLEW                 => "FAST"
	)
	port map
	(
		O                    => CNVp, 
		OB                   => CNVn,
		I                    => CNV
	);

process begin
	wait until rising_edge(CLK100);
	counter_100              <= counter_100 + 1;
	if counter_100 = 19 then
		counter_100          <= 0;
	end if;

	CLK_D_p                  <= CLK_data(counter_100*2 + 1);
	CLK_D_n                  <= CLK_data(counter_100*2);
	
	CNV_D_p                  <= CNV_data(counter_100*2 + 1);
	CNV_D_n                  <= CNV_data(counter_100*2);

	data_ready               <= '0';
	if counter_100 = 19 then
		data_ready           <= '1';
		data                 <= data_buffer;
	end if;
end process;

process begin
	wait until rising_edge(DCO);
	data_buffer              <= data_buffer(14 downto 0) & D;
end process;

end;