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-- Company: 
-- Engineer: 
-- 
-- Create Date: 19.02.2022 17:24:10
-- Design Name: 
-- Module Name: main - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library ieee;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    PORT(
    CLK100MHZ: IN STD_LOGIC;
    HSYNC, VSYNC: OUT STD_LOGIC;
    VgaR,VgaG,VgaB: OUT STD_LOGIC_VECTOR(3 downto 0)
    );
    
end main;



architecture Behavioral of main is

-- Horozontal timing (values in px or 65MHz clock ticks)
constant HorizontalSyncPulse : integer := 136;
constant HorizontalBackporch : integer := 160;
constant HorizontalVisibleArea : integer := 1024;
constant HorizontalFrontporch : integer := 24;

-- Vertical timing (values in lines)
constant VerticalSyncPulse : integer := 6;
constant VerticalBackporch : integer := 29;
constant VerticalVisibleArea : integer := 768;
constant VerticalFrontporch : integer := 3;

-- Current position
signal HPos: integer range 0 to 1343:=0;
signal VPos: integer range 0 to 805:=0;

signal CLK65MHz: STD_LOGIC;


-- Telling the compiler that there is a component called "clk_wiz_0" and what inputs and outputs it has
component clk_wiz_0 is
    port(
        clk_in1: in std_logic;
        clk_out1: out std_logic
        );
end component;

begin

-- there is an instance of that clockwiz component called "clkwiz0" and mapping its inputs and outputs
clkwiz0: clk_wiz_0
    port map(clk_in1 => CLK100MHZ,
      clk_out1 => CLK65MHz);

process(CLK65MHz)
begin
    if rising_edge(CLK65MHz) then
        -- do this every rising clock edge
        if HPos < 1343 then
            -- increment the HPos value if we are not at the end of a line
            HPos <= HPos + 1;
        else
            HPOS <= 0;
            if VPos < 805 then
                -- increment the VPos value if a line has been completed and we are not at the end of the entire frame
                VPos <= VPos + 1;
            else
                VPos <= 0;
            end if;
        end if;
    

        -- Generate the horizontal sync pulse

        if HPos < HorizontalSyncPulse then
            HSync <= '0';
        end if;

        if HPos >= HorizontalSyncPulse  then
            HSync <= '1';
        end if;

        -- generate the vertical sync pulse

        if VPos < VerticalSyncPulse then
            VSync <= '0';
        end if;

        if VPos >= VerticalSyncPulse then
            VSync <= '1';
        end if;

        -- Check if we are in the actual frame area

        if ((HPos >= (HorizontalSyncPulse+HorizontalBackporch)) AND (HPos < (HorizontalSyncPulse+HorizontalBackporch+HorizontalVisibleArea))) then
            -- we are in the frame ara, in terms of horizontal position
    
            if((VPos >= (VerticalSyncPulse+VerticalBackporch)) AND (VPos < (VerticalSyncPulse+VerticalBackporch+VerticalVisibleArea))) then
                -- we are in the frame are, in terms of vertical position
                -- so we are in the actual frame area
        
                --output a blue screen
                VgaR <= "0000";
                VgaG <= "0000";
                VgaB <= "1111";
            end if;

        end if;
    end if;

end process;

end architecture;