Property Type Read-only Value ALLOWED_SIM_MODELS string* true rtl BASE_BOARD_PART string true xilinx.com:zcu106:part0:2.5 BOARD string true xilinx.com:zcu106:part0:2.5 BOARD_CONNECTIONS string true CLASS string true ip COMBINED_SIM_MODEL string false rtl CONFIG.CHANNEL_ENABLE string false X0Y5 X0Y4 CONFIG.Component_Name string false gtwizard_ultrascale_0 CONFIG.DISABLE_LOC_XDC string false 0 CONFIG.ENABLE_COMMON_USRCLK string false 0 CONFIG.ENABLE_OPTIONAL_PORTS string false CONFIG.FREERUN_FREQUENCY string false 250 CONFIG.GT_DIRECTION string false BOTH CONFIG.GT_REV string false 0 CONFIG.GT_TYPE string false GTH CONFIG.INCLUDE_CPLL_CAL string false 2 CONFIG.INS_LOSS_NYQ string false 14 CONFIG.INTERNAL_PRESET string false Aurora_8B10B CONFIG.LOCATE_COMMON string false EXAMPLE_DESIGN CONFIG.LOCATE_IN_SYSTEM_IBERT_CORE string false NONE CONFIG.LOCATE_RESET_CONTROLLER string false CORE CONFIG.LOCATE_RX_BUFFER_BYPASS_CONTROLLER string false CORE CONFIG.LOCATE_RX_USER_CLOCKING string false EXAMPLE_DESIGN CONFIG.LOCATE_TX_BUFFER_BYPASS_CONTROLLER string false CORE CONFIG.LOCATE_TX_USER_CLOCKING string false EXAMPLE_DESIGN CONFIG.LOCATE_USER_DATA_WIDTH_SIZING string false CORE CONFIG.OOB_ENABLE string false false CONFIG.ORGANIZE_PORTS_BY string false NAME CONFIG.PCIE_64BIT string false false CONFIG.PCIE_CORECLK_FREQ string false 250 CONFIG.PCIE_ENABLE string false false CONFIG.PCIE_GEN4_EIOS string false false CONFIG.PCIE_USERCLK_FREQ string false 250 CONFIG.PRESET string false GTH-Aurora_8B10B CONFIG.RESET_SEQUENCE_INTERVAL string false 0 CONFIG.RX_BUFFER_BYPASS_MODE string false MULTI CONFIG.RX_BUFFER_MODE string false 1 CONFIG.RX_BUFFER_RESET_ON_CB_CHANGE string false ENABLE CONFIG.RX_BUFFER_RESET_ON_COMMAALIGN string false DISABLE CONFIG.RX_BUFFER_RESET_ON_RATE_CHANGE string false ENABLE CONFIG.RX_CB_DISP_0_0 string false false CONFIG.RX_CB_DISP_0_1 string false false CONFIG.RX_CB_DISP_0_2 string false false CONFIG.RX_CB_DISP_0_3 string false false CONFIG.RX_CB_DISP_1_0 string false false CONFIG.RX_CB_DISP_1_1 string false false CONFIG.RX_CB_DISP_1_2 string false false CONFIG.RX_CB_DISP_1_3 string false false CONFIG.RX_CB_K_0_0 string false true CONFIG.RX_CB_K_0_1 string false false CONFIG.RX_CB_K_0_2 string false false CONFIG.RX_CB_K_0_3 string false false CONFIG.RX_CB_K_1_0 string false false CONFIG.RX_CB_K_1_1 string false false CONFIG.RX_CB_K_1_2 string false false CONFIG.RX_CB_K_1_3 string false false CONFIG.RX_CB_LEN_SEQ string false 1 CONFIG.RX_CB_MASK_0_0 string false false CONFIG.RX_CB_MASK_0_1 string false false CONFIG.RX_CB_MASK_0_2 string false false CONFIG.RX_CB_MASK_0_3 string false false CONFIG.RX_CB_MASK_1_0 string false false CONFIG.RX_CB_MASK_1_1 string false false CONFIG.RX_CB_MASK_1_2 string false false CONFIG.RX_CB_MASK_1_3 string false false CONFIG.RX_CB_MAX_LEVEL string false 1 CONFIG.RX_CB_MAX_SKEW string false 7 CONFIG.RX_CB_NUM_SEQ string false 1 CONFIG.RX_CB_VAL_0_0 string false 01111100 CONFIG.RX_CB_VAL_0_1 string false 00000000 CONFIG.RX_CB_VAL_0_2 string false 00000000 CONFIG.RX_CB_VAL_0_3 string false 00000000 CONFIG.RX_CB_VAL_1_0 string false 00000000 CONFIG.RX_CB_VAL_1_1 string false 00000000 CONFIG.RX_CB_VAL_1_2 string false 00000000 CONFIG.RX_CB_VAL_1_3 string false 00000000 CONFIG.RX_CC_DISP_0_0 string false false CONFIG.RX_CC_DISP_0_1 string false false CONFIG.RX_CC_DISP_0_2 string false false CONFIG.RX_CC_DISP_0_3 string false false CONFIG.RX_CC_DISP_1_0 string false false CONFIG.RX_CC_DISP_1_1 string false false CONFIG.RX_CC_DISP_1_2 string false false CONFIG.RX_CC_DISP_1_3 string false false CONFIG.RX_CC_KEEP_IDLE string false DISABLE CONFIG.RX_CC_K_0_0 string false true CONFIG.RX_CC_K_0_1 string false true CONFIG.RX_CC_K_0_2 string false false CONFIG.RX_CC_K_0_3 string false false CONFIG.RX_CC_K_1_0 string false false CONFIG.RX_CC_K_1_1 string false false CONFIG.RX_CC_K_1_2 string false false CONFIG.RX_CC_K_1_3 string false false CONFIG.RX_CC_LEN_SEQ string false 2 CONFIG.RX_CC_MASK_0_0 string false false CONFIG.RX_CC_MASK_0_1 string false false CONFIG.RX_CC_MASK_0_2 string false false CONFIG.RX_CC_MASK_0_3 string false false CONFIG.RX_CC_MASK_1_0 string false false CONFIG.RX_CC_MASK_1_1 string false false CONFIG.RX_CC_MASK_1_2 string false false CONFIG.RX_CC_MASK_1_3 string false false CONFIG.RX_CC_NUM_SEQ string false 1 CONFIG.RX_CC_PERIODICITY string false 5000 CONFIG.RX_CC_PRECEDENCE string false ENABLE CONFIG.RX_CC_REPEAT_WAIT string false 0 CONFIG.RX_CC_VAL string false 00000000000000000000000000000000000000000000000000000000000000111101110011110111 CONFIG.RX_CC_VAL_0_0 string false 11110111 CONFIG.RX_CC_VAL_0_1 string false 11110111 CONFIG.RX_CC_VAL_0_2 string false 00000000 CONFIG.RX_CC_VAL_0_3 string false 00000000 CONFIG.RX_CC_VAL_1_0 string false 00000000 CONFIG.RX_CC_VAL_1_1 string false 00000000 CONFIG.RX_CC_VAL_1_2 string false 00000000 CONFIG.RX_CC_VAL_1_3 string false 00000000 CONFIG.RX_COMMA_ALIGN_WORD string false 2 CONFIG.RX_COMMA_DOUBLE_ENABLE string false false CONFIG.RX_COMMA_MASK string false 1111111111 CONFIG.RX_COMMA_M_ENABLE string false true CONFIG.RX_COMMA_M_VAL string false 1010000011 CONFIG.RX_COMMA_PRESET string false K28.5 CONFIG.RX_COMMA_P_ENABLE string false true CONFIG.RX_COMMA_P_VAL string false 0101111100 CONFIG.RX_COMMA_SHOW_REALIGN_ENABLE string false true CONFIG.RX_COMMA_VALID_ONLY string false 0 CONFIG.RX_COUPLING string false AC CONFIG.RX_DATA_DECODING string false 8B10B CONFIG.RX_EQ_MODE string false AUTO CONFIG.RX_INT_DATA_WIDTH string false 40 CONFIG.RX_JTOL_FC string false 9.3731254 CONFIG.RX_JTOL_LF_SLOPE string false -20 CONFIG.RX_LINE_RATE string false 15.625 CONFIG.RX_MASTER_CHANNEL string false X0Y5 CONFIG.RX_OUTCLK_SOURCE string false RXOUTCLKPMA CONFIG.RX_PLL_TYPE string false QPLL0 CONFIG.RX_PPM_OFFSET string false 200 CONFIG.RX_QPLL_FRACN_NUMERATOR string false 0 CONFIG.RX_RECCLK_OUTPUT string false CONFIG.RX_REFCLK_FREQUENCY string false 156.25 CONFIG.RX_REFCLK_SOURCE string false CONFIG.RX_SLIDE_MODE string false OFF CONFIG.RX_SSC_PPM string false 0 CONFIG.RX_TERMINATION string false PROGRAMMABLE CONFIG.RX_TERMINATION_PROG_VALUE string false 800 CONFIG.RX_USER_DATA_WIDTH string false 32 CONFIG.SATA_TX_BURST_LEN string false 15 CONFIG.SECONDARY_QPLL_ENABLE string false false CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR string false 0 CONFIG.SECONDARY_QPLL_LINE_RATE string false 10.3125 CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY string false 257.8125 CONFIG.SIM_CPLL_CAL_BYPASS string false 1 CONFIG.TXPROGDIV_FREQ_ENABLE string false false CONFIG.TXPROGDIV_FREQ_SOURCE string false QPLL0 CONFIG.TXPROGDIV_FREQ_VAL string false 390.625 CONFIG.TX_BUFFER_MODE string false 1 CONFIG.TX_BUFFER_RESET_ON_RATE_CHANGE string false ENABLE CONFIG.TX_DATA_ENCODING string false 8B10B CONFIG.TX_DIFF_SWING_EMPH_MODE string false CUSTOM CONFIG.TX_INT_DATA_WIDTH string false 40 CONFIG.TX_LINE_RATE string false 15.625 CONFIG.TX_MASTER_CHANNEL string false X0Y5 CONFIG.TX_OUTCLK_SOURCE string false TXOUTCLKPMA CONFIG.TX_PLL_TYPE string false QPLL0 CONFIG.TX_QPLL_FRACN_NUMERATOR string false 0 CONFIG.TX_REFCLK_FREQUENCY string false 156.25 CONFIG.TX_REFCLK_SOURCE string false CONFIG.TX_USER_DATA_WIDTH string false 32 CONFIG.USB_ENABLE string false false CONFIG.USER_GTPOWERGOOD_DELAY_EN string false 1 CORE_REVISION int true 8 DELIVERED_TARGETS string* true instantiation_template DESIGN_TOOL_CONTEXTS string* true HDL IPI Sysgen IPDEF string true xilinx.com:ip:gtwizard_ultrascale:1.7 IP_CORE_CONTAINER string true IP_DIR string true /home/baumannt/devel/workspaceSYD/jtag-example/work/flexistage_b2b_jtag_example.srcs/sources_1/ip/gtwizard_ultrascale_0 IP_FILE string true /home/baumannt/devel/workspaceSYD/jtag-example/work/flexistage_b2b_jtag_example.srcs/sources_1/ip/gtwizard_ultrascale_0/gtwizard_ultrascale_0.xci IS_BD_CONTEXT bool true 0 IS_LOCKED bool true 0 KNOWN_TARGETS string* true instantiation_template synthesis simulation example changelog NAME string true gtwizard_ultrascale_0 PART string true xczu7ev-ffvc1156-2-e SELECTED_SIM_MODEL string false rtl STALE_TARGETS string* true instantiation_template SUPPORTED_TARGETS string* true instantiation_template synthesis simulation example changelog SUPPORTS_MODREF bool true 0 SW_VERSION string true 2020.1 UNSUPPORTED_SIMULATORS string* true USED_LICENSE_KEYS string* true USER_LOCKED bool false 0