---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:57:19 07/07/2009 -- Design Name: -- Module Name: log2 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity log2 is port ( clk : in std_logic; reset : in std_logic; start : in std_logic; din : in std_logic_vector (15 downto 0); dout : out std_logic_vector (12 downto 0); drdy : out std_logic; logzero : out std_logic ); end log2; architecture Behavioral of log2 is type STATES is (STATE_WAIT, STATE_SHIFT, STATE_LUT, STATE_LUT_2); signal ram_addr : std_logic_vector (7 downto 0); signal ram_data : std_logic_vector (8 downto 0); component log_rom is port ( addr : in std_logic_vector(7 downto 0); dout : out std_logic_vector(8 downto 0) ); end component; begin log_rom0: log_rom port map ( addr => ram_addr, dout => ram_data ); process (clk) variable state : STATES := STATE_WAIT; variable sr : std_logic_vector (15 downto 0); variable ctr : unsigned (3 downto 0) := X"F"; begin if clk'event and clk='1' then if reset='1' then ctr := X"F"; sr := (others => '0'); state := STATE_WAIT; drdy <= '0'; logzero <= '0'; else case state is when STATE_WAIT => logzero <= '0'; drdy <= '0'; ctr := X"F"; if start='1' then if din=X"0000" then -- log(0) geht nicht! logzero <= '1'; dout <= (others => '0'); drdy <= '1'; else state := STATE_SHIFT; sr := din; end if; end if; when STATE_SHIFT => if sr(15) = '1' then ram_addr <= sr(14 downto 7); state := STATE_LUT; else sr := sr(14 downto 0) & '0'; ctr := ctr-1; end if; when STATE_LUT => state := STATE_LUT_2; -- kompatibilität zu altera wegen BRAM when STATE_LUT_2 => dout(12 downto 9) <= std_logic_vector(ctr); dout(8 downto 0) <= ram_data; drdy <= '1'; state := STATE_WAIT; when others => state := STATE_WAIT; end case; end if; end if; end process; end Behavioral;