cpldfit: version G.36 Xilinx Inc. Fitter Report Design Name: mmb Date: 1-11-2005, 0:39AM Device Used: XC9536-5-VQ44 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 33 /36 ( 92%) 80 /180 ( 44%) 16 /36 ( 44%) 34 /34 (100%) 55 /72 ( 76%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 10 10 | I/O : 28 0 Output : 8 8 | GCK/IO : 3 0 Bidirectional : 16 16 | GTS/IO : 2 0 GCK : 0 0 | GSR/IO : 1 0 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 34 34 MACROCELL RESOURCES: Total Macrocells Available 36 Registered Macrocells 16 Non-registered Macrocell driving I/O 16 GLOBAL RESOURCES: Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. POWER DATA: There are 33 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 33 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State $OpTx$FX_DC$1 2 2 FB1_7 STD 1 GCK/I/O I AVR_AD<0> 4 12 FB2_3 STD FAST 36 GTS/I/O I/O AVR_AD<1> 4 12 FB2_4 STD FAST 37 I/O I/O AVR_AD<2> 4 12 FB2_2 STD FAST 38 I/O I/O AVR_AD<3> 4 12 FB2_1 STD FAST 39 I/O I/O AVR_AD<4> 4 12 FB1_1 STD FAST 40 I/O I/O AVR_AD<5> 4 12 FB1_2 STD FAST 41 I/O I/O AVR_AD<6> 4 12 FB1_4 STD FAST 42 I/O I/O AVR_AD<7> 4 12 FB1_3 STD FAST 43 GCK/I/O I/O Bank_Reg<0> 2 10 FB1_18 STD (b) (b) RESET Bank_Reg<1> 2 10 FB1_14 STD 13 I/O I RESET Bank_Reg<2> 2 10 FB1_13 STD 12 I/O I RESET Bank_Reg<3> 2 10 FB1_12 STD 8 I/O I RESET Bank_Reg<4> 2 10 FB1_11 STD 7 I/O I RESET Bank_Reg<5> 2 10 FB1_10 STD 6 I/O I RESET Bank_Reg<6> 2 10 FB1_9 STD 5 I/O I RESET Bank_Reg<7> 2 10 FB1_8 STD 3 I/O I RESET FTDI_RD 1 9 FB2_12 STD FAST 27 I/O O FTDI_WR 1 9 FB2_11 STD FAST 28 I/O O MMD_CS<0> 1 8 FB2_10 STD FAST 29 I/O O MMD_CS<1> 3 8 FB2_9 STD FAST 30 I/O O SPI_CS<0> 2 10 FB1_15 STD FAST 14 I/O I/O RESET SPI_CS<1> 2 10 FB1_16 STD FAST 16 I/O I/O RESET SPI_CS<2> 2 10 FB1_17 STD FAST 18 I/O I/O RESET SPI_CS<3> 2 10 FB2_17 STD FAST 19 I/O I/O RESET SPI_CS<4> 2 10 FB2_16 STD FAST 20 I/O I/O RESET SPI_CS<5> 2 10 FB2_15 STD FAST 21 I/O I/O RESET SPI_CS<6> 2 10 FB2_14 STD FAST 22 I/O I/O RESET SPI_CS<7> 2 10 FB2_13 STD FAST 23 I/O I/O RESET SRAM_AH<0> 2 3 FB2_5 STD FAST 34 GTS/I/O O SRAM_AH<1> 2 3 FB2_6 STD FAST 33 GSR/I/O O SRAM_AH<2> 2 3 FB2_7 STD FAST 32 I/O O SRAM_AH<3> 2 3 FB2_8 STD FAST 31 I/O O ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use AVR_AH<0> FB1_5 44 GCK/I/O I AVR_AH<1> FB1_7 1 GCK/I/O I AVR_AH<2> FB1_6 2 I/O I AVR_AH<3> FB1_8 3 I/O I AVR_AH<4> FB1_9 5 I/O I AVR_AH<5> FB1_10 6 I/O I AVR_AH<6> FB1_11 7 I/O I AVR_AH<7> FB1_12 8 I/O I AVR_RD FB1_14 13 I/O I AVR_WR FB1_13 12 I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 16 27 27 40 0/7 17 FB2 17 28 28 40 8/9 17 ---- ----- ----- ----- 33 80 8/16 34 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 27/9 Number of signals used by logic mapping into function block: 27 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use AVR_AD<4> 4 0 0 1 FB1_1 STD 40 I/O I/O AVR_AD<5> 4 0 0 1 FB1_2 STD 41 I/O I/O AVR_AD<7> 4 0 0 1 FB1_3 STD 43 GCK/I/O I/O AVR_AD<6> 4 0 0 1 FB1_4 STD 42 I/O I/O (unused) 0 0 0 5 FB1_5 44 GCK/I/O I (unused) 0 0 0 5 FB1_6 2 I/O I $OpTx$FX_DC$1 2 0 0 3 FB1_7 STD 1 GCK/I/O I Bank_Reg<7> 2 0 0 3 FB1_8 STD 3 I/O I Bank_Reg<6> 2 0 0 3 FB1_9 STD 5 I/O I Bank_Reg<5> 2 0 0 3 FB1_10 STD 6 I/O I Bank_Reg<4> 2 0 0 3 FB1_11 STD 7 I/O I Bank_Reg<3> 2 0 0 3 FB1_12 STD 8 I/O I Bank_Reg<2> 2 0 0 3 FB1_13 STD 12 I/O I Bank_Reg<1> 2 0 0 3 FB1_14 STD 13 I/O I SPI_CS<0> 2 0 0 3 FB1_15 STD 14 I/O I/O SPI_CS<1> 2 0 0 3 FB1_16 STD 16 I/O I/O SPI_CS<2> 2 0 0 3 FB1_17 STD 18 I/O I/O Bank_Reg<0> 2 0 0 3 FB1_18 STD (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$1 10: AVR_RD 19: AVR_AD<3>.PIN 2: AVR_AH<0> 11: AVR_WR 20: AVR_AD<4>.PIN 3: AVR_AH<1> 12: Bank_Reg<4> 21: AVR_AD<5>.PIN 4: AVR_AH<2> 13: Bank_Reg<5> 22: AVR_AD<6>.PIN 5: AVR_AH<3> 14: Bank_Reg<6> 23: AVR_AD<7>.PIN 6: AVR_AH<4> 15: Bank_Reg<7> 24: SPI_CS<4>.PIN 7: AVR_AH<5> 16: AVR_AD<0>.PIN 25: SPI_CS<5>.PIN 8: AVR_AH<6> 17: AVR_AD<1>.PIN 26: SPI_CS<6>.PIN 9: AVR_AH<7> 18: AVR_AD<2>.PIN 27: SPI_CS<7>.PIN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs AVR_AD<4> XXXXXXXXXX.X...........X................ 12 12 AVR_AD<5> XXXXXXXXXX..X...........X............... 12 12 AVR_AD<7> XXXXXXXXXX....X...........X............. 12 12 AVR_AD<6> XXXXXXXXXX...X...........X.............. 12 12 $OpTx$FX_DC$1 .XX..................................... 2 2 Bank_Reg<7> .XXXXXXXX.X...........X................. 10 10 Bank_Reg<6> .XXXXXXXX.X..........X.................. 10 10 Bank_Reg<5> .XXXXXXXX.X.........X................... 10 10 Bank_Reg<4> .XXXXXXXX.X........X.................... 10 10 Bank_Reg<3> .XXXXXXXX.X.......X..................... 10 10 Bank_Reg<2> .XXXXXXXX.X......X...................... 10 10 Bank_Reg<1> .XXXXXXXX.X.....X....................... 10 10 SPI_CS<0> .XXXXXXXX.X....X........................ 10 10 SPI_CS<1> .XXXXXXXX.X.....X....................... 10 10 SPI_CS<2> .XXXXXXXX.X......X...................... 10 10 Bank_Reg<0> .XXXXXXXX.X....X........................ 10 10 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 28/8 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use AVR_AD<3> 4 0 0 1 FB2_1 STD 39 I/O I/O AVR_AD<2> 4 0 0 1 FB2_2 STD 38 I/O I/O AVR_AD<0> 4 0 0 1 FB2_3 STD 36 GTS/I/O I/O AVR_AD<1> 4 0 0 1 FB2_4 STD 37 I/O I/O SRAM_AH<0> 2 0 0 3 FB2_5 STD 34 GTS/I/O O SRAM_AH<1> 2 0 0 3 FB2_6 STD 33 GSR/I/O O SRAM_AH<2> 2 0 0 3 FB2_7 STD 32 I/O O SRAM_AH<3> 2 0 0 3 FB2_8 STD 31 I/O O MMD_CS<1> 3 0 0 2 FB2_9 STD 30 I/O O MMD_CS<0> 1 0 0 4 FB2_10 STD 29 I/O O FTDI_WR 1 0 0 4 FB2_11 STD 28 I/O O FTDI_RD 1 0 0 4 FB2_12 STD 27 I/O O SPI_CS<7> 2 0 0 3 FB2_13 STD 23 I/O I/O SPI_CS<6> 2 0 0 3 FB2_14 STD 22 I/O I/O SPI_CS<5> 2 0 0 3 FB2_15 STD 21 I/O I/O SPI_CS<4> 2 0 0 3 FB2_16 STD 20 I/O I/O SPI_CS<3> 2 0 0 3 FB2_17 STD 19 I/O I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$1 11: AVR_WR 20: AVR_AD<3>.PIN 2: AVR_AH<0> 12: Bank_Reg<0> 21: AVR_AD<4>.PIN 3: AVR_AH<1> 13: Bank_Reg<1> 22: AVR_AD<5>.PIN 4: AVR_AH<2> 14: Bank_Reg<2> 23: AVR_AD<6>.PIN 5: AVR_AH<3> 15: Bank_Reg<3> 24: AVR_AD<7>.PIN 6: AVR_AH<4> 16: Bank_Reg<4> 25: SPI_CS<0>.PIN 7: AVR_AH<5> 17: Bank_Reg<5> 26: SPI_CS<1>.PIN 8: AVR_AH<6> 18: Bank_Reg<6> 27: SPI_CS<2>.PIN 9: AVR_AH<7> 19: Bank_Reg<7> 28: SPI_CS<3>.PIN 10: AVR_RD Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs AVR_AD<3> XXXXXXXXXX....X............X............ 12 12 AVR_AD<2> XXXXXXXXXX...X............X............. 12 12 AVR_AD<0> XXXXXXXXXX.X............X............... 12 12 AVR_AD<1> XXXXXXXXXX..X............X.............. 12 12 SRAM_AH<0> ........X..X...X........................ 3 3 SRAM_AH<1> ........X...X...X....................... 3 3 SRAM_AH<2> ........X....X...X...................... 3 3 SRAM_AH<3> ........X.....X...X..................... 3 3 MMD_CS<1> .XXXXXXXX............................... 8 8 MMD_CS<0> .XXXXXXXX............................... 8 8 FTDI_WR .XXXXXXXX.X............................. 9 9 FTDI_RD .XXXXXXXXX.............................. 9 9 SPI_CS<7> .XXXXXXXX.X............X................ 10 10 SPI_CS<6> .XXXXXXXX.X...........X................. 10 10 SPI_CS<5> .XXXXXXXX.X..........X.................. 10 10 SPI_CS<4> .XXXXXXXX.X.........X................... 10 10 SPI_CS<3> .XXXXXXXX.X........X.................... 10 10 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. $OpTx$FX_DC$1 <= AVR_AH(0) XOR $OpTx$FX_DC$1 <= AVR_AH(1); AVR_AD_I(0) <= ((NOT AVR_AH(0) AND SPI_CS(0).PIN) OR (AVR_AH(1) AND SPI_CS(0).PIN) OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(0))); AVR_AD(0) <= AVR_AD_I(0) when AVR_AD_OE(0) = '1' else 'Z'; AVR_AD_OE(0) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1); AVR_AD_I(1) <= ((NOT AVR_AH(0) AND SPI_CS(1).PIN) OR (AVR_AH(1) AND SPI_CS(1).PIN) OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(1))); AVR_AD(1) <= AVR_AD_I(1) when AVR_AD_OE(1) = '1' else 'Z'; AVR_AD_OE(1) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1); AVR_AD_I(2) <= ((NOT AVR_AH(0) AND SPI_CS(2).PIN) OR (AVR_AH(1) AND SPI_CS(2).PIN) OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(2))); AVR_AD(2) <= AVR_AD_I(2) when AVR_AD_OE(2) = '1' else 'Z'; AVR_AD_OE(2) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1); AVR_AD_I(3) <= ((NOT AVR_AH(0) AND SPI_CS(3).PIN) OR (AVR_AH(1) AND SPI_CS(3).PIN) OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(3))); AVR_AD(3) <= AVR_AD_I(3) when AVR_AD_OE(3) = '1' else 'Z'; AVR_AD_OE(3) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1); AVR_AD_I(4) <= ((NOT AVR_AH(0) AND SPI_CS(4).PIN) OR (AVR_AH(1) AND SPI_CS(4).PIN) OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(4))); AVR_AD(4) <= AVR_AD_I(4) when AVR_AD_OE(4) = '1' else 'Z'; AVR_AD_OE(4) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1); AVR_AD_I(5) <= ((NOT AVR_AH(0) AND SPI_CS(5).PIN) OR (AVR_AH(1) AND SPI_CS(5).PIN) OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(5))); AVR_AD(5) <= AVR_AD_I(5) when AVR_AD_OE(5) = '1' else 'Z'; AVR_AD_OE(5) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1); AVR_AD_I(6) <= ((NOT AVR_AH(0) AND SPI_CS(6).PIN) OR (AVR_AH(1) AND SPI_CS(6).PIN) OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(6))); AVR_AD(6) <= AVR_AD_I(6) when AVR_AD_OE(6) = '1' else 'Z'; AVR_AD_OE(6) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1); AVR_AD_I(7) <= ((NOT AVR_AH(0) AND SPI_CS(7).PIN) OR (AVR_AH(1) AND SPI_CS(7).PIN) OR (AVR_AH(0) AND NOT AVR_AH(1) AND Bank_Reg(7))); AVR_AD(7) <= AVR_AD_I(7) when AVR_AD_OE(7) = '1' else 'Z'; AVR_AD_OE(7) <= (AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND $OpTx$FX_DC$1); FDCPE_Bank_Reg0: FDCPE port map (Bank_Reg(0),'0','0',Bank_Reg_CLR(0),Bank_Reg_PRE(0)); Bank_Reg_CLR(0) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND NOT AVR_AD(0).PIN AND NOT AVR_WR); Bank_Reg_PRE(0) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND AVR_AD(0).PIN AND NOT AVR_WR); FDCPE_Bank_Reg1: FDCPE port map (Bank_Reg(1),'0','0',Bank_Reg_CLR(1),Bank_Reg_PRE(1)); Bank_Reg_CLR(1) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND NOT AVR_AD(1).PIN AND NOT AVR_WR); Bank_Reg_PRE(1) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND AVR_AD(1).PIN AND NOT AVR_WR); FDCPE_Bank_Reg2: FDCPE port map (Bank_Reg(2),'0','0',Bank_Reg_CLR(2),Bank_Reg_PRE(2)); Bank_Reg_CLR(2) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND NOT AVR_AD(2).PIN AND NOT AVR_WR); Bank_Reg_PRE(2) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND AVR_AD(2).PIN AND NOT AVR_WR); FDCPE_Bank_Reg3: FDCPE port map (Bank_Reg(3),'0','0',Bank_Reg_CLR(3),Bank_Reg_PRE(3)); Bank_Reg_CLR(3) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND NOT AVR_AD(3).PIN AND NOT AVR_WR); Bank_Reg_PRE(3) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND AVR_AD(3).PIN AND NOT AVR_WR); FDCPE_Bank_Reg4: FDCPE port map (Bank_Reg(4),'0','0',Bank_Reg_CLR(4),Bank_Reg_PRE(4)); Bank_Reg_CLR(4) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND NOT AVR_AD(4).PIN AND NOT AVR_WR); Bank_Reg_PRE(4) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND AVR_AD(4).PIN AND NOT AVR_WR); FDCPE_Bank_Reg5: FDCPE port map (Bank_Reg(5),'0','0',Bank_Reg_CLR(5),Bank_Reg_PRE(5)); Bank_Reg_CLR(5) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND NOT AVR_AD(5).PIN AND NOT AVR_WR); Bank_Reg_PRE(5) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND AVR_AD(5).PIN AND NOT AVR_WR); FDCPE_Bank_Reg6: FDCPE port map (Bank_Reg(6),'0','0',Bank_Reg_CLR(6),Bank_Reg_PRE(6)); Bank_Reg_CLR(6) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND NOT AVR_AD(6).PIN AND NOT AVR_WR); Bank_Reg_PRE(6) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND AVR_AD(6).PIN AND NOT AVR_WR); FDCPE_Bank_Reg7: FDCPE port map (Bank_Reg(7),'0','0',Bank_Reg_CLR(7),Bank_Reg_PRE(7)); Bank_Reg_CLR(7) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND NOT AVR_AD(7).PIN AND NOT AVR_WR); Bank_Reg_PRE(7) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND NOT AVR_AH(1) AND AVR_AD(7).PIN AND NOT AVR_WR); FTDI_RD <= NOT ((AVR_AH(4) AND NOT AVR_RD AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND AVR_AH(1))); FTDI_WR <= NOT ((AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND AVR_AH(0) AND AVR_AH(1) AND NOT AVR_WR)); MMD_CS(0) <= NOT ((AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND AVR_AH(2) AND NOT AVR_AH(0) AND NOT AVR_AH(1))); MMD_CS(1) <= ((NOT AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5)) OR (NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2)) OR (NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(0) AND NOT AVR_AH(1))); FDCPE_SPI_CS0: FDCPE port map (SPI_CS(0),'0','0',SPI_CS_CLR(0),SPI_CS_PRE(0)); SPI_CS_CLR(0) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND NOT AVR_AD(0).PIN AND NOT AVR_WR); SPI_CS_PRE(0) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND AVR_AD(0).PIN AND NOT AVR_WR); FDCPE_SPI_CS1: FDCPE port map (SPI_CS(1),'0','0',SPI_CS_CLR(1),SPI_CS_PRE(1)); SPI_CS_CLR(1) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND NOT AVR_AD(1).PIN AND NOT AVR_WR); SPI_CS_PRE(1) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND AVR_AD(1).PIN AND NOT AVR_WR); FDCPE_SPI_CS2: FDCPE port map (SPI_CS(2),'0','0',SPI_CS_CLR(2),SPI_CS_PRE(2)); SPI_CS_CLR(2) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND NOT AVR_AD(2).PIN AND NOT AVR_WR); SPI_CS_PRE(2) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND AVR_AD(2).PIN AND NOT AVR_WR); FDCPE_SPI_CS3: FDCPE port map (SPI_CS(3),'0','0',SPI_CS_CLR(3),SPI_CS_PRE(3)); SPI_CS_CLR(3) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND NOT AVR_AD(3).PIN AND NOT AVR_WR); SPI_CS_PRE(3) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND AVR_AD(3).PIN AND NOT AVR_WR); FDCPE_SPI_CS4: FDCPE port map (SPI_CS(4),'0','0',SPI_CS_CLR(4),SPI_CS_PRE(4)); SPI_CS_CLR(4) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND NOT AVR_AD(4).PIN AND NOT AVR_WR); SPI_CS_PRE(4) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND AVR_AD(4).PIN AND NOT AVR_WR); FDCPE_SPI_CS5: FDCPE port map (SPI_CS(5),'0','0',SPI_CS_CLR(5),SPI_CS_PRE(5)); SPI_CS_CLR(5) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND NOT AVR_AD(5).PIN AND NOT AVR_WR); SPI_CS_PRE(5) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND AVR_AD(5).PIN AND NOT AVR_WR); FDCPE_SPI_CS6: FDCPE port map (SPI_CS(6),'0','0',SPI_CS_CLR(6),SPI_CS_PRE(6)); SPI_CS_CLR(6) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND NOT AVR_AD(6).PIN AND NOT AVR_WR); SPI_CS_PRE(6) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND AVR_AD(6).PIN AND NOT AVR_WR); FDCPE_SPI_CS7: FDCPE port map (SPI_CS(7),'0','0',SPI_CS_CLR(7),SPI_CS_PRE(7)); SPI_CS_CLR(7) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND NOT AVR_AD(7).PIN AND NOT AVR_WR); SPI_CS_PRE(7) <= (AVR_AH(4) AND NOT AVR_AH(7) AND NOT AVR_AH(6) AND NOT AVR_AH(5) AND NOT AVR_AH(3) AND NOT AVR_AH(2) AND NOT AVR_AH(0) AND AVR_AH(1) AND AVR_AD(7).PIN AND NOT AVR_WR); SRAM_AH(0) <= ((AVR_AH(7) AND Bank_Reg(4)) OR (NOT AVR_AH(7) AND Bank_Reg(0))); SRAM_AH(1) <= ((AVR_AH(7) AND Bank_Reg(5)) OR (NOT AVR_AH(7) AND Bank_Reg(1))); SRAM_AH(2) <= ((AVR_AH(7) AND Bank_Reg(6)) OR (NOT AVR_AH(7) AND Bank_Reg(2))); SRAM_AH(3) <= ((AVR_AH(7) AND Bank_Reg(7)) OR (NOT AVR_AH(7) AND Bank_Reg(3))); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); **************************** Device Pin Out **************************** Device : XC9536-5-VQ44 ----------------------------------- /44 43 42 41 40 39 38 37 36 35 34 33 \ | 1 32 | | 2 31 | | 3 30 | | 4 29 | | 5 XC9536-5-VQ44 28 | | 6 27 | | 7 26 | | 8 25 | | 9 24 | | 10 23 | | 11 22 | \ 12 13 14 15 16 17 18 19 20 21 22 23 / ----------------------------------- Pin Signal Pin Signal No. Name No. Name 1 AVR_AH<1> 23 SPI_CS<7> 2 AVR_AH<2> 24 TDO 3 AVR_AH<3> 25 GND 4 GND 26 VCC 5 AVR_AH<4> 27 FTDI_RD 6 AVR_AH<5> 28 FTDI_WR 7 AVR_AH<6> 29 MMD_CS<0> 8 AVR_AH<7> 30 MMD_CS<1> 9 TDI 31 SRAM_AH<3> 10 TMS 32 SRAM_AH<2> 11 TCK 33 SRAM_AH<1> 12 AVR_WR 34 SRAM_AH<0> 13 AVR_RD 35 VCC 14 SPI_CS<0> 36 AVR_AD<0> 15 VCC 37 AVR_AD<1> 16 SPI_CS<1> 38 AVR_AD<2> 17 GND 39 AVR_AD<3> 18 SPI_CS<2> 40 AVR_AD<4> 19 SPI_CS<3> 41 AVR_AD<5> 20 SPI_CS<4> 42 AVR_AD<6> 21 SPI_CS<5> 43 AVR_AD<7> 22 SPI_CS<6> 44 AVR_AH<0> Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536-5-VQ44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25