/* -------------------------------------------------------------------------- TCE - 16-bit Timer/Counter Type E -------------------------------------------------------------------------- */ /* 16-bit Timer/Counter Type E */ typedef struct TCE_struct { register8_t CTRLA; /* Control A */ register8_t CTRLB; /* Control B */ register8_t CTRLC; /* Control C */ register8_t CTRLD; /* Control D */ register8_t CTRLECLR; /* Control E Clear */ register8_t CTRLESET; /* Control E Set */ register8_t CTRLFCLR; /* Control F Clear */ register8_t CTRLFSET; /* Control F Set */ register8_t EVGENCTRL; /* Event Generation Control */ register8_t EVCTRL; /* Event Control */ register8_t INTCTRL; /* Interrupt Control */ register8_t INTFLAGS; /* Interrupt Flags */ register8_t reserved_1[2]; register8_t DBGCTRL; /* Debug Control */ register8_t TEMP; /* Temporary data for 16-bit Access */ register8_t reserved_2[16]; _WORDREGISTER(CNT); /* Count */ _WORDREGISTER(AMP); /* Amplitude */ _WORDREGISTER(OFFSET); /* Offset */ _WORDREGISTER(PER); /* Period */ _WORDREGISTER(CMP0); /* Compare 0 */ _WORDREGISTER(CMP1); /* Compare 1 */ _WORDREGISTER(CMP2); /* Compare 2 */ _WORDREGISTER(CMP3); /* Compare 3 */ register8_t reserved_3[6]; _WORDREGISTER(PERBUF); /* Period Buffer */ _WORDREGISTER(CMP0BUF); /* Compare 0 Buffer */ _WORDREGISTER(CMP1BUF); /* Compare 1 Buffer */ _WORDREGISTER(CMP2BUF); /* Compare 2 Buffer */ _WORDREGISTER(CMP3BUF); /* Compare 3 Buffer */ } TCE_t; /* Clock Selection */ typedef enum TCE_CLKSEL_enum { TCE_CLKSEL_DIV1_gc = (0x00<<1), /* System Clock */ TCE_CLKSEL_DIV2_gc = (0x01<<1), /* System Clock / 2 */ TCE_CLKSEL_DIV4_gc = (0x02<<1), /* System Clock / 4 */ TCE_CLKSEL_DIV8_gc = (0x03<<1), /* System Clock / 8 */ TCE_CLKSEL_DIV16_gc = (0x04<<1), /* System Clock / 16 */ TCE_CLKSEL_DIV64_gc = (0x05<<1), /* System Clock / 64 */ TCE_CLKSEL_DIV256_gc = (0x06<<1), /* System Clock / 256 */ TCE_CLKSEL_DIV1024_gc = (0x07<<1) /* System Clock / 1024 */ } TCE_CLKSEL_t; /* Command select */ typedef enum TCE_CMD_enum { TCE_CMD_NONE_gc = (0x00<<2), /* No Command */ TCE_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ TCE_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ TCE_CMD_RESET_gc = (0x03<<2) /* Force Hard Reset */ } TCE_CMD_t; /* Compare # Event select */ typedef enum TCE_CMP0EV_enum { TCE_CMP0EV_PULSE_gc = (0x00<<4), /* Event output for CMP is a pulse */ TCE_CMP0EV_WAVEFORM_gc = (0x01<<4) /* Event output for CMP is equal to waveform */ } TCE_CMP0EV_t; /* Compare # Event select */ typedef enum TCE_CMP1EV_enum { TCE_CMP1EV_PULSE_gc = (0x00<<5), /* Event output for CMP is a pulse */ TCE_CMP1EV_WAVEFORM_gc = (0x01<<5) /* Event output for CMP is equal to waveform */ } TCE_CMP1EV_t; /* Compare # Event select */ typedef enum TCE_CMP2EV_enum { TCE_CMP2EV_PULSE_gc = (0x00<<6), /* Event output for CMP is a pulse */ TCE_CMP2EV_WAVEFORM_gc = (0x01<<6) /* Event output for CMP is equal to waveform */ } TCE_CMP2EV_t; /* Compare # Event select */ typedef enum TCE_CMP3EV_enum { TCE_CMP3EV_PULSE_gc = (0x00<<7), /* Event output for CMP is a pulse */ TCE_CMP3EV_WAVEFORM_gc = (0x01<<7) /* Event output for CMP is equal to waveform */ } TCE_CMP3EV_t; /* Direction select */ typedef enum TCE_DIR_enum { TCE_DIR_UP_gc = (0x00<<0), /* Count up */ TCE_DIR_DOWN_gc = (0x01<<0) /* Count down */ } TCE_DIR_t; /* Event Action A select */ typedef enum TCE_EVACTA_enum { TCE_EVACTA_CNT_POSEDGE_gc = (0x00<<1), /* Count on positive edge event */ TCE_EVACTA_CNT_ANYEDGE_gc = (0x01<<1), /* Count on any edge event */ TCE_EVACTA_CNT_HIGHLVL_gc = (0x02<<1), /* Count on prescaled clock while event line is 1. */ TCE_EVACTA_UPDOWN_gc = (0x03<<1) /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ } TCE_EVACTA_t; /* Event Action B select */ typedef enum TCE_EVACTB_enum { TCE_EVACTB_NONE_gc = (0x00<<5), /* No Action */ TCE_EVACTB_UPDOWN_gc = (0x03<<5), /* Count on prescaled clock. Event controls count direction. Up-count when event line is 0, down-count when event line is 1. */ TCE_EVACTB_RESTART_POSEDGE_gc = (0x04<<5), /* Restart counter at positive edge event */ TCE_EVACTB_RESTART_ANYEDGE_gc = (0x05<<5), /* Restart counter on any edge event */ TCE_EVACTB_RESTART_HIGHLVL_gc = (0x06<<5) /* Restart counter while event line is 1. */ } TCE_EVACTB_t; /* High Resolution Enable select */ typedef enum TCE_HREN_enum { TCE_HREN_OFF_gc = (0x00<<6), /* High Resolution Disable */ TCE_HREN_4X_gc = (0x01<<6), /* Resolution increased by 4 (2 bits) */ TCE_HREN_8X_gc = (0x02<<6) /* Resolution increased by 4 (3 bits) */ } TCE_HREN_t; /* Scaled Write select */ typedef enum TCE_SCALE_enum { TCE_SCALE_NORMAL_gc = (0x00<<2), /* Absolute values used when writing to CMPn, CMPnBUF and registers */ TCE_SCALE_FRACTIONAL_gc = (0x01<<2) /* Fractional values used when writing to CMPn, CMPnBUF and registers */ } TCE_SCALE_t; /* Scaling Mode select */ typedef enum TCE_SCALEMODE_enum { TCE_SCALEMODE_CENTER_gc = (0x00<<4), /* CMPn registers scaled vs center (50% duty cycle) */ TCE_SCALEMODE_BOTTOM_gc = (0x01<<4), /* CMPn registers scaled vs BOTTOM (0% duty cycle) */ TCE_SCALEMODE_TOP_gc = (0x02<<4), /* CMPn registers scaled vs TOP (100% duty cycle) */ TCE_SCALEMODE_TOPBOTTOM_gc = (0x03<<4) /* CMPn registers scaled vs TOP or BOTTOM depending on written value. */ } TCE_SCALEMODE_t; /* Waveform generation mode select */ typedef enum TCE_WGMODE_enum { TCE_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ TCE_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ TCE_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope PWM */ TCE_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope PWM, overflow on TOP */ TCE_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope PWM, overflow on TOP and BOTTOM */ TCE_WGMODE_DSBOTTOM_gc = (0x07<<0) /* Dual Slope PWM, overflow on BOTTOM */ } TCE_WGMODE_t;