library ieee;
use ieee.std_logic_1164.all;

entity tgate is
    port (
        a       : inout std_logic;
        b       : inout std_logic;
        control : in    std_logic);
end entity tgate;

architecture func_behav of tgate is
begin

    p : process is
    begin
        wait on A, B, control;
        A <= 'Z';
        B <= 'Z';
        wait for 0 ns;
        if control = '1' then
            A <= B;
            B <= A;
            wait for 0 ns;
        elsif control = 'X' then
            A <= 'X';
            B <= 'X';
            wait for 0 ns;
        end if;
    end process p;

end architecture func_behav;