library ieee;
use ieee.std_logic_1164.all;

entity tb is

end entity tb;

architecture sim of tb is
    signal a        : std_logic;
    signal b        : std_logic;
    signal control  : std_logic;
    signal a_driver : std_logic;
    signal b_driver : std_logic;
begin  -- architecture sim
    tgate_1 : entity work.tgate
        port map (
            a       => a,
            b       => b,
            control => control);

    -- Connect drivers to a / b for easier debugging
    a <= a_driver;
    b <= b_driver;

    test : process is
    begin
        a_driver <= 'Z';
        b_driver <= '1';
        control  <= '0';
        wait for 10 ns;
        control  <= '1';
        wait for 10 ns;
        b_driver <= '0';
        wait for 10 ns;
        a_driver <= '0';
        wait for 10 ns;
        a_driver <= '1';
        wait for 10 ns;
        control  <= '0';
        wait for 10 ns;
        a_driver <= 'Z';
        b_driver <= 'Z';
        wait for 10 ns;
        control  <= '1';
        wait for 10 ns;
        wait;
    end process test;

end architecture sim;