library ieee; use ieee.std_logic_1164.all; entity atari_tb is end entity atari_tb; architecture testbench of atari_tb is signal simulation_run : boolean := true; -- constant tb_phi2_frequency : natural := 2_000_000; constant tb_phi2_period : time := 1 sec / tb_phi2_frequency; -- constant tb_clk50_frequency : natural := 50_000_000; constant tb_clk50_period : time := 1 sec / tb_clk50_frequency; signal tb_adr : std_logic_vector(15 downto 0); -- ATARI Adressbus signal tb_data : std_logic_vector(7 downto 0); -- ATARI Datenbus signal tb_ram_rom_adr : std_logic_vector(18 downto 0); -- Externer SRAM/(E)EPROM Adressbus signal tb_data_en : std_logic; -- Enable Data-Bustreiber signal tb_data_dir : std_logic; -- Direction Data-Bustreiber LO=ATARI zum FPGA. HI=FPGA zum ATARI signal tb_adress_en : std_logic; -- Enable Adress-Bustreiber signal tb_adress_dir : std_logic; -- Direction Adress-Bustreiber LO=ATARI zum FPGA. HI=FPGA zum ATARI signal tb_ram0_ce : std_logic; -- CE vom SRAM0 signal tb_ram1_ce : std_logic; -- CE vom SRAM1 (zusätzliches Pad zum Huckepack RAM) signal tb_ram_oe : std_logic; -- OE vom SRAM signal tb_ramrom_we : std_logic; -- WE vom SRAM und EEPROM signal tb_rom_ce : std_logic; -- CE vom (E)EPROM signal tb_rom_oe : std_logic; -- OE vom (E)EPROM signal tb_rdy : std_logic; -- RDY Signal vom ATARI, nicht benutzt signal tb_rw : std_logic; -- ATARI R/W signal tb_audio : std_logic; -- zum PBI Audio Eingang via 100nF signal tb_segment7 : std_logic_vector(7 downto 0); -- Segmente a-g der 7Segment Anzeigen und 8Bits für LEDs signal tb_display7 : std_logic_vector(14 downto 1); -- 7Segment Anzeigen, LEDs und Schalter/Taster signal tb_switch_in : std_logic; -- HI aktiver Schalter Eingang signal tb_phi2 : std_logic := '0'; -- ATARI Clock signal tb_phi2short : std_logic; -- verkürzte ATARI Clock durch 74123 signal tb_reset_n_in : std_logic; -- Reseteingang signal tb_trigger : std_logic; -- Triggerausgang mit verlängerten Signal(74HCT123) für z.B. Freezer / Bibomon signal tb_IRQ : std_logic; -- IRQ Ausgang, um den ATARI zu bremsen (über BC847 Transistor) signal tb_clk50 : std_logic := '0'; -- 50Mhz Oszillator signal tb_gpio : std_logic_vector(13 downto 0); -- freie IOs, rechte Seite ab Layout V3 signal tb_gpin : std_logic_vector(1 downto 0); -- freie INs, rechte Seite ab Layout V3 signal tb_refresh : std_logic; -- Refreshausgang, um eigene Zugriffe auf den Bus zu ermöglichen (über BC847 Transistor) begin tb_adr <= ( others => '0'); tb_data <= ( others => 'Z'); tb_ram_rom_adr <= ( others => 'Z'); tb_rdy <= '0'; tb_rw <= '1'; tb_switch_in <= '0'; tb_phi2 <= not tb_phi2 after tb_phi2_period / 2 when simulation_run; tb_phi2short <= tb_phi2; tb_reset_n_in <= '0', '1' after 10 * tb_phi2_period; tb_clk50 <= not tb_clk50 after tb_clk50_period / 2 when simulation_run; tb_gpio <= ( others => 'Z'); tb_gpin <= "00"; dut: entity work.ATARI_PBI_FPGA port map ( adr => tb_adr, --: in std_logic_vector(15 downto 0); -- ATARI Adressbus data => tb_data, --: inout std_logic_vector(7 downto 0); -- ATARI Datenbus ram_rom_adr => tb_ram_rom_adr,--: inout std_logic_vector(18 downto 0); -- Externer SRAM/(E)EPROM Adressbus data_en => tb_data_en, --: out std_logic := '1'; -- Enable Data-Bustreiber data_dir => tb_data_dir, --: out std_logic := '0'; -- Direction Data-Bustreiber LO=ATARI zum FPGA. HI=FPGA zum ATARI adress_en => tb_adress_en, --: out std_logic := '1'; -- Enable Adress-Bustreiber adress_dir => tb_adress_dir, --: out std_logic := '0'; -- Direction Adress-Bustreiber LO=ATARI zum FPGA. HI=FPGA zum ATARI ram0_ce => tb_ram0_ce, --: out std_logic := '1'; -- CE vom SRAM0 ram1_ce => tb_ram1_ce, --: out std_logic := '1'; -- CE vom SRAM1 (zusätzliches Pad zum Huckepack RAM) ram_oe => tb_ram_oe, --: out std_logic := '1'; -- OE vom SRAM ramrom_we => tb_ramrom_we, --: out std_logic := '1'; -- WE vom SRAM und EEPROM rom_ce => tb_rom_ce, --: out std_logic := '1'; -- CE vom (E)EPROM rom_oe => tb_rom_oe, --: out std_logic := '1'; -- OE vom (E)EPROM rdy => tb_rdy, --: in std_logic; -- RDY Signal vom ATARI, nicht benutzt rw => tb_rw, --: in std_logic; -- ATARI R/W audio => tb_audio, --: out std_logic; -- zum PBI Audio Eingang via 100nF segment7 => tb_segment7, --: out std_logic_vector(7 downto 0); -- Segmente a-g der 7Segment Anzeigen und 8Bits für LEDs display7 => tb_display7, --: out std_logic_vector(14 downto 1); -- 7Segment Anzeigen, LEDs und Schalter/Taster switch_in => tb_switch_in, --: in std_logic := '0'; -- HI aktiver Schalter Eingang phi2 => tb_phi2, --: in std_logic; -- ATARI Clock phi2short => tb_phi2short, --: in std_logic; -- verkürzte ATARI Clock durch 74123 reset_n_in => tb_reset_n_in, --: in std_logic; -- Reseteingang trigger => tb_trigger, --: out std_logic := '0'; -- Triggerausgang mit verlängerten Signal(74HCT123) für z.B. Freezer / Bibomon IRQ => tb_IRQ, --: out std_logic := '0'; -- IRQ Ausgang, um den ATARI zu bremsen (über BC847 Transistor) clk50 => tb_clk50, --: in std_logic; -- 50Mhz Oszillator gpio => tb_gpio, --: inout std_logic_vector(13 downto 0); -- freie IOs, rechte Seite ab Layout V3 gpin => tb_gpin, --: in std_logic_vector(1 downto 0); -- freie INs, rechte Seite ab Layout V3 refresh => tb_refresh --: out std_logic := '0' -- Refreshausgang, um eigene Zugriffe auf den Bus zu ermöglichen (über BC847 Transistor) ); main: process begin wait for 1 ms; simulation_run <= false; report "Simulation end."; wait; end process; end architecture testbench;