library ieee;
use ieee.std_logic_1164.all;

entity taktteiler_tb is
end entity taktteiler_tb;


architecture testbench of taktteiler_tb is

    constant phi2_frequency     : natural   := 1770000;
    constant phi2_period        : time      := 1 sec / phi2_frequency;

    constant clk50_frequency    : natural   := 50000000;
    constant clk50_period       : time      := 1 sec / clk50_frequency;

    signal  simulation_run      : boolean   := true;
    
    signal tb_clk50             : std_logic := '0'; -- IO17 clock 50MHz
    signal tb_phi2              : std_logic := '0'; -- PHI2 clock 1.77MHz
    --                          
    signal tb_phi2short         : std_logic;        -- PHI2 shorted clock 1.77MHz

begin

    tb_clk50    <= not tb_clk50 after clk50_period  / 2 when simulation_run;
    tb_phi2     <= not tb_phi2  after phi2_period   / 2 when simulation_run;

    dut: entity work.taktteiler
    port map
    (
        clk50       => tb_clk50,    --: in std_logic;  -- IO17 clock 50MHz
        phi2        => tb_phi2,     --: in std_logic;  -- PHI2 clock 1.77MHz
        --
        phi2short   => tb_phi2short --: out std_logic; -- PHI2 shorted clock 1.77MHz
    );

    process
    begin
        wait for 2 us;
        simulation_run  <= false;
        report "Simulation end.";
        wait;
    end process;
end architecture testbench;