library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity freqcount is
  port (
    clk      : in  std_logic;
    rst_n    : in  std_logic;
    --
    data_i   : in  std_logic;
    countm_o : out std_logic_vector(30 downto 0));
end entity;

architecture rtl of freqcount is

  signal cnt        : std_logic_vector(27 downto 0);
  signal cnt_time   : std_logic_vector(27 downto 0);
  signal data_i_old : std_logic;

begin

  process (clk, rst_n)
  begin
    if rst_n = '0' then
      cnt_time   <= (others => '0');
      cnt        <= (others => '0');
      countm_o   <= (others => '0');
      data_i_old <= '0';
    elsif rising_edge(clk) then
      data_i_old <= data_i;
      if to_integer(unsigned(cnt_time)) >= 25_000_000 then  --restart counting
        countm_o <= "0" & cnt & "00";
        cnt_time <= (others => '0');
        cnt      <= (others => '0');
      else                                                  --counting
        cnt_time <= std_logic_vector(to_unsigned(to_integer(unsigned(cnt_time)) +1, 28));
        if data_i_old = '0' and data_i = '1' then
          cnt <= std_logic_vector(to_unsigned(to_integer(unsigned(cnt)) + 1, 28));
        else
          cnt <= cnt;
        end if;
      end if;
    end if;
  end process;
end architecture;