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-- Company: www.Circuit-Break.de
-- Engineer: Jens Weiss
-- 
-- Create Date:    10:14:32 02/23/2024 
-- Design Name: 
-- Module Name:    Opcode_memory - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity Opcode_memory is
	Generic(ADRESSWIDTH : natural := 5;	--memory depth = 2^ADDRESSWIDTH
				  DATAWIDTH : natural := 8);
				  
	Port	(	clk	: in std_logic;
				A		: in std_logic_vector(ADRESSWIDTH-1 downto 0);
				Dout	: out std_logic_vector(DATAWIDTH-1 downto 0)
			);
end Opcode_memory;

architecture Behavioral of Opcode_memory is

	signal RomAddr  : integer range 0 to (2**ADRESSWIDTH)-1;	
	type Rom is array (0 to (2**ADRESSWIDTH)-1) of STD_LOGIC_VECTOR(DATAWIDTH-1 downto 0); 
	constant Parameter_Rom : Rom := (
-- Integrator LT1
 	 "00101000",  -- Ocode: "00101 000"		Parameter: b1 | Dataselect: 000 (data_in)
	 "00000001",  -- Ocode: "00000 001"		Parameter: a1 | Dataselect: 001 (int_data_out)
	 "10100011",  -- Ocode: "10100 011"		Parameter:e21 | Dataselect: 011 (LT2_out)
	 "10101100",  -- Ocode: "10101 100"		Parameter:e31 | Dataselect: 100 (LT3_out)
	 "10111101",  -- Ocode: "10111 101"		Parameter:e41 | Dataselect: 101 (LT4_out)
-- Integrator LT2
	 "00110000",  -- Ocode: "00110 000"		Parameter: b2 | Dataselect: 000 (data_in)
	 "00001001",  -- Ocode: "00001 001"		Parameter: a2 | Dataselect: 001 (int_data_out)
	 "01010010",  -- Ocode: "01010 010"		Parameter: c1 | Dataselect: 010 (LT1_out)
	 "10110100",  -- Ocode: "10110 100"		Parameter:e32 | Dataselect: 100 (LT3_out)
	 "11000101",  -- Ocode: "11000 101"		Parameter:e42 | Dataselect: 101 (LT4_out)
-- Integrator LT3
	 "00111000",  -- Ocode: "00111 000"		Parameter: b3 | Dataselect: 000 (data_in)
	 "00010001",  -- Ocode: "00010 001"		Parameter: a3 | Dataselect: 001 (int_data_out)
	 "01110010",  -- Ocode: "01110 010"		Parameter:d13 | Dataselect: 010 (LT1_out)
	 "01011011",  -- Ocode: "01011 011"		Parameter: c2 | Dataselect: 011 (LT2_out)
	 "11001101",  -- Ocode: "11001 101"		Parameter:e43 | Dataselect: 101 (LT4_out)
-- Integrator LT4
	 "01000000",  -- Ocode: "01000 000"		Parameter: b4 | Dataselect: 000 (data_in)
	 "00011001",  -- Ocode: "00011 001"		Parameter: a4 | Dataselect: 001 (int_data_out)
	 "01111010",  -- Ocode: "01111 010"		Parameter:d14 | Dataselect: 010 (LT1_out)
	 "10001011",  -- Ocode: "10001 011"		Parameter:d24 | Dataselect: 011 (LT2_out)
	 "01100100",  -- Ocode: "01100 100"		Parameter: c3 | Dataselect: 100 (LT3_out)	 
-- Output/to Quantizer
	 "01001000",  -- Ocode: "01001 000"		Parameter: b5 | Dataselect: 000 (data_in)
	 "00100001",  -- Ocode: "00100 001"		Parameter: a5 | Dataselect: 001 (int_data_out)
	 "10000010",  -- Ocode: "10000 010"		Parameter:d15 | Dataselect: 010 (LT1_out)
	 "10010011",  -- Ocode: "10010 011"		Parameter:d25 | Dataselect: 011 (LT2_out)
	 "10011100",  -- Ocode: "10011 100"		Parameter:d35 | Dataselect: 100 (LT3_out)
	 "01101101",  -- Ocode: "01101 101"		Parameter: c4 | Dataselect: 101 (LT4_out)
	 others => "00000000"
	 );	 

begin
	--BROM      
   process begin
     wait until rising_edge(clk);
     RomAddr <= to_integer(unsigned(A)); -- clocked address --> BRAM
   end process;
   --Dout <= Parameter_Rom(to_integer(unsigned(A)));
	Dout <= std_logic_vector(Parameter_Rom(RomAddr));

end Behavioral;