library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Genereller Einsynchronisierungsblock mit 2 Register delay sowie 3 Register fuer Flankendetektion
-- Lizenz: GPLv3

entity Eint is
    port (
        clk:            in std_logic;
        rst_n:          in std_logic;
        pin_i:       in std_logic; 
        posedge_o:         out std_logic; -- 3 clk delay
		data_o:			out std_logic; -- 2 clk delay
		negedge_o:		out std_logic -- 3 clk delay
    );

end entity;

architecture rtl of Eint is

signal data_i_old: std_logic;
signal data_i_old_old: std_logic;

begin
    process (clk, rst_n)
    begin
    if rst_n = '0' then
		data_i_old <= '0';
		data_i_old_old <= '0';
	elsif rising_edge(clk) then
		data_i_old<=pin_i; --register1
		data_i_old_old<=data_i_old; --register2
		data_o<=data_i_old; --use different register to reduce load
		if(data_i_old_old = '0' and data_i_old = '1') then
			posedge_o <= '1';
		else
			posedge_o <= '0';
		end if;
		if(data_i_old_old = '1' and data_i_old = '0') then
			negedge_o <= '1';
		else
			negedge_o <= '0';
		end if;
    end if;
    end process;
end architecture;