: TWI_Master_t twiMaster; /*!< TWI master module. */ int main(void) { 26: df 93 push r29 28: cf 93 push r28 2a: cd b7 in r28, 0x3d ; 61 2c: de b7 in r29, 0x3e ; 62 2e: 2a 97 sbiw r28, 0x0a ; 10 30: cd bf out 0x3d, r28 ; 61 32: de bf out 0x3e, r29 ; 62 /*! Buffer with test data to send.*/ uint8_t sendBuffer[] = {0x07,0x00,0xff}; 34: ce 01 movw r24, r28 36: 01 96 adiw r24, 0x01 ; 1 38: 8e 83 std Y+6, r24 ; 0x06 3a: 9f 83 std Y+7, r25 ; 0x07 3c: e0 e0 ldi r30, 0x00 ; 0 3e: f0 e2 ldi r31, 0x20 ; 32 40: e8 87 std Y+8, r30 ; 0x08 42: f9 87 std Y+9, r31 ; 0x09 44: f3 e0 ldi r31, 0x03 ; 3 46: fa 87 std Y+10, r31 ; 0x0a 48: e8 85 ldd r30, Y+8 ; 0x08 4a: f9 85 ldd r31, Y+9 ; 0x09 4c: 00 80 ld r0, Z 4e: 88 85 ldd r24, Y+8 ; 0x08 50: 99 85 ldd r25, Y+9 ; 0x09 52: 01 96 adiw r24, 0x01 ; 1 54: 88 87 std Y+8, r24 ; 0x08 56: 99 87 std Y+9, r25 ; 0x09 58: ee 81 ldd r30, Y+6 ; 0x06 5a: ff 81 ldd r31, Y+7 ; 0x07 5c: 00 82 st Z, r0 5e: 8e 81 ldd r24, Y+6 ; 0x06 60: 9f 81 ldd r25, Y+7 ; 0x07 62: 01 96 adiw r24, 0x01 ; 1 64: 8e 83 std Y+6, r24 ; 0x06 66: 9f 83 std Y+7, r25 ; 0x07 68: 9a 85 ldd r25, Y+10 ; 0x0a 6a: 91 50 subi r25, 0x01 ; 1 6c: 9a 87 std Y+10, r25 ; 0x0a 6e: ea 85 ldd r30, Y+10 ; 0x0a 70: ee 23 and r30, r30 72: 51 f7 brne .-44 ; 0x48 <__SREG__+0x9> uint8_t sendBuffer2[] = {0x03,0x00}; 74: 83 e0 ldi r24, 0x03 ; 3 76: 8c 83 std Y+4, r24 ; 0x04 78: 1d 82 std Y+5, r1 ; 0x05 /* Initialize PORTE for output and PORTD for inverted input. */ PORTF.DIRSET = 0b00000100; 7a: e0 ea ldi r30, 0xA0 ; 160 7c: f6 e0 ldi r31, 0x06 ; 6 7e: 84 e0 ldi r24, 0x04 ; 4 80: 81 83 std Z+1, r24 ; 0x01 PORTF.OUTCLR= 0b00000100; 82: e0 ea ldi r30, 0xA0 ; 160 84: f6 e0 ldi r31, 0x06 ; 6 86: 84 e0 ldi r24, 0x04 ; 4 88: 86 83 std Z+6, r24 ; 0x06 /* Initialize TWI master. */ TWI_MasterInit(&twiMaster,&TWID,TWI_MASTER_INTLVL_LO_gc,TWI_BAUDSETTING); 8a: 84 e0 ldi r24, 0x04 ; 4 8c: 90 e2 ldi r25, 0x20 ; 32 8e: 60 e9 ldi r22, 0x90 ; 144 90: 74 e0 ldi r23, 0x04 ; 4 92: 40 e4 ldi r20, 0x40 ; 64 94: 25 e0 ldi r18, 0x05 ; 5 96: 0e 94 c4 00 call 0x188 ; 0x188 /* Initialize TWI slave. */ /* Enable LO interrupt level. */ PMIC.CTRL |= PMIC_LOLVLEN_bm; 9a: a0 ea ldi r26, 0xA0 ; 160 9c: b0 e0 ldi r27, 0x00 ; 0 9e: e0 ea ldi r30, 0xA0 ; 160 a0: f0 e0 ldi r31, 0x00 ; 0 a2: 82 81 ldd r24, Z+2 ; 0x02 a4: 81 60 ori r24, 0x01 ; 1 a6: 12 96 adiw r26, 0x02 ; 2 a8: 8c 93 st X, r24 aa: 12 97 sbiw r26, 0x02 ; 2 sei(); ac: 78 94 sei while (twiMaster.status != TWIM_STATUS_READY) { ae: 80 91 16 20 lds r24, 0x2016 b2: 88 23 and r24, r24 b4: e1 f7 brne .-8 ; 0xae <__SREG__+0x6f> /* Wait until transaction is complete. */ } TWI_MasterWrite(&twiMaster,SLAVE_ADDRESS,sendBuffer,3); b6: 84 e0 ldi r24, 0x04 ; 4 b8: 90 e2 ldi r25, 0x20 ; 32 ba: 60 e2 ldi r22, 0x20 ; 32 bc: 9e 01 movw r18, r28 be: 2f 5f subi r18, 0xFF ; 255 c0: 3f 4f sbci r19, 0xFF ; 255 c2: a9 01 movw r20, r18 c4: 23 e0 ldi r18, 0x03 ; 3 c6: 0e 94 1b 01 call 0x236 ; 0x236 while (twiMaster.status != TWIM_STATUS_READY) { ca: 80 91 16 20 lds r24, 0x2016 ce: 88 23 and r24, r24 d0: e1 f7 brne .-8 ; 0xca <__SREG__+0x8b> /* Wait until transaction is complete. */ } TWI_MasterWrite(&twiMaster,SLAVE_ADDRESS,sendBuffer2,2); d2: 84 e0 ldi r24, 0x04 ; 4 d4: 90 e2 ldi r25, 0x20 ; 32 d6: 9e 01 movw r18, r28 d8: 2c 5f subi r18, 0xFC ; 252 da: 3f 4f sbci r19, 0xFF ; 255 dc: 60 e2 ldi r22, 0x20 ; 32 de: a9 01 movw r20, r18 e0: 22 e0 ldi r18, 0x02 ; 2 e2: 0e 94 1b 01 call 0x236 ; 0x236 while (twiMaster.status != TWIM_STATUS_READY) { e6: 80 91 16 20 lds r24, 0x2016 ea: 88 23 and r24, r24 ec: e1 f7 brne .-8 ; 0xe6 <__SREG__+0xa7> ee: ff cf rjmp .-2 ; 0xee <__SREG__+0xaf> 000000f0 <__vector_76>: return 0; } /*! TWIC Master Interrupt vector. */ ISR(TWID_TWIM_vect) { f0: 1f 92 push r1 f2: 0f 92 push r0 f4: 0f b6 in r0, 0x3f ; 63 f6: 0f 92 push r0 f8: 00 90 38 00 lds r0, 0x0038 fc: 0f 92 push r0 fe: 00 90 39 00 lds r0, 0x0039 102: 0f 92 push r0 104: 00 90 3b 00 lds r0, 0x003B 108: 0f 92 push r0 10a: 11 24 eor r1, r1 10c: 10 92 38 00 sts 0x0038, r1 110: 10 92 39 00 sts 0x0039, r1 114: 10 92 3b 00 sts 0x003B, r1 118: 2f 93 push r18 11a: 3f 93 push r19 11c: 4f 93 push r20 11e: 5f 93 push r21 120: 6f 93 push r22 122: 7f 93 push r23 124: 8f 93 push r24 126: 9f 93 push r25 128: af 93 push r26 12a: bf 93 push r27 12c: ef 93 push r30 12e: ff 93 push r31 130: df 93 push r29 132: cf 93 push r28 134: cd b7 in r28, 0x3d ; 61 136: de b7 in r29, 0x3e ; 62 PORTF.OUTSET= 0b00000100; 138: e0 ea ldi r30, 0xA0 ; 160 13a: f6 e0 ldi r31, 0x06 ; 6 13c: 84 e0 ldi r24, 0x04 ; 4 13e: 85 83 std Z+5, r24 ; 0x05 TWI_MasterInterruptHandler(&twiMaster); 140: 84 e0 ldi r24, 0x04 ; 4 142: 90 e2 ldi r25, 0x20 ; 32 144: 0e 94 df 01 call 0x3be ; 0x3be PORTF.OUTCLR= 0b00000100; 148: e0 ea ldi r30, 0xA0 ; 160 14a: f6 e0 ldi r31, 0x06 ; 6 14c: 84 e0 ldi r24, 0x04 ; 4 14e: 86 83 std Z+6, r24 ; 0x06 } 150: cf 91 pop r28 152: df 91 pop r29 154: ff 91 pop r31 156: ef 91 pop r30 158: bf 91 pop r27 15a: af 91 pop r26 15c: 9f 91 pop r25 15e: 8f 91 pop r24 160: 7f 91 pop r23 162: 6f 91 pop r22 164: 5f 91 pop r21 166: 4f 91 pop r20 168: 3f 91 pop r19 16a: 2f 91 pop r18 16c: 0f 90 pop r0 16e: 00 92 3b 00 sts 0x003B, r0 172: 0f 90 pop r0 174: 00 92 39 00 sts 0x0039, r0 178: 0f 90 pop r0 17a: 00 92 38 00 sts 0x0038, r0 17e: 0f 90 pop r0 180: 0f be out 0x3f, r0 ; 63 182: 0f 90 pop r0 184: 1f 90 pop r1 186: 18 95 reti 00000188 : */ void TWI_MasterInit(TWI_Master_t *twi, TWI_t *module, TWI_MASTER_INTLVL_t intLevel, uint8_t baudRateRegisterSetting) { 188: df 93 push r29 18a: cf 93 push r28 18c: 00 d0 rcall .+0 ; 0x18e 18e: 00 d0 rcall .+0 ; 0x190 190: cd b7 in r28, 0x3d ; 61 192: de b7 in r29, 0x3e ; 62 194: 89 83 std Y+1, r24 ; 0x01 196: 9a 83 std Y+2, r25 ; 0x02 198: 6b 83 std Y+3, r22 ; 0x03 19a: 7c 83 std Y+4, r23 ; 0x04 19c: 4d 83 std Y+5, r20 ; 0x05 19e: 2e 83 std Y+6, r18 ; 0x06 twi->interface = module; 1a0: e9 81 ldd r30, Y+1 ; 0x01 1a2: fa 81 ldd r31, Y+2 ; 0x02 1a4: 8b 81 ldd r24, Y+3 ; 0x03 1a6: 9c 81 ldd r25, Y+4 ; 0x04 1a8: 80 83 st Z, r24 1aa: 91 83 std Z+1, r25 ; 0x01 twi->interface->MASTER.CTRLA = intLevel | 1ac: e9 81 ldd r30, Y+1 ; 0x01 1ae: fa 81 ldd r31, Y+2 ; 0x02 1b0: 01 90 ld r0, Z+ 1b2: f0 81 ld r31, Z 1b4: e0 2d mov r30, r0 1b6: 8d 81 ldd r24, Y+5 ; 0x05 1b8: 88 63 ori r24, 0x38 ; 56 1ba: 81 83 std Z+1, r24 ; 0x01 TWI_MASTER_RIEN_bm | TWI_MASTER_WIEN_bm | TWI_MASTER_ENABLE_bm; twi->interface->MASTER.BAUD = baudRateRegisterSetting; 1bc: e9 81 ldd r30, Y+1 ; 0x01 1be: fa 81 ldd r31, Y+2 ; 0x02 1c0: 01 90 ld r0, Z+ 1c2: f0 81 ld r31, Z 1c4: e0 2d mov r30, r0 1c6: 8e 81 ldd r24, Y+6 ; 0x06 1c8: 85 83 std Z+5, r24 ; 0x05 twi->interface->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc; 1ca: e9 81 ldd r30, Y+1 ; 0x01 1cc: fa 81 ldd r31, Y+2 ; 0x02 1ce: 01 90 ld r0, Z+ 1d0: f0 81 ld r31, Z 1d2: e0 2d mov r30, r0 1d4: 81 e0 ldi r24, 0x01 ; 1 1d6: 84 83 std Z+4, r24 ; 0x04 } 1d8: 26 96 adiw r28, 0x06 ; 6 1da: cd bf out 0x3d, r28 ; 61 1dc: de bf out 0x3e, r29 ; 62 1de: cf 91 pop r28 1e0: df 91 pop r29 1e2: 08 95 ret 000001e4 : * \retval TWI_MASTER_BUSSTATE_IDLE_gc Bus state is idle. * \retval TWI_MASTER_BUSSTATE_OWNER_gc Bus state is owned by the master. * \retval TWI_MASTER_BUSSTATE_BUSY_gc Bus state is busy. */ TWI_MASTER_BUSSTATE_t TWI_MasterState(TWI_Master_t *twi) { 1e4: df 93 push r29 1e6: cf 93 push r28 1e8: 00 d0 rcall .+0 ; 0x1ea 1ea: cd b7 in r28, 0x3d ; 61 1ec: de b7 in r29, 0x3e ; 62 1ee: 8a 83 std Y+2, r24 ; 0x02 1f0: 9b 83 std Y+3, r25 ; 0x03 TWI_MASTER_BUSSTATE_t twi_status; twi_status = (TWI_MASTER_BUSSTATE_t) (twi->interface->MASTER.STATUS & 1f2: ea 81 ldd r30, Y+2 ; 0x02 1f4: fb 81 ldd r31, Y+3 ; 0x03 1f6: 01 90 ld r0, Z+ 1f8: f0 81 ld r31, Z 1fa: e0 2d mov r30, r0 1fc: 84 81 ldd r24, Z+4 ; 0x04 1fe: 83 70 andi r24, 0x03 ; 3 200: 89 83 std Y+1, r24 ; 0x01 TWI_MASTER_BUSSTATE_gm); return twi_status; 202: 89 81 ldd r24, Y+1 ; 0x01 } 204: 23 96 adiw r28, 0x03 ; 3 206: cd bf out 0x3d, r28 ; 61 208: de bf out 0x3e, r29 ; 62 20a: cf 91 pop r28 20c: df 91 pop r29 20e: 08 95 ret 00000210 : * * \retval true If transaction could be started. * \retval false If transaction could not be started. */ bool TWI_MasterReady(TWI_Master_t *twi) { 210: df 93 push r29 212: cf 93 push r28 214: 00 d0 rcall .+0 ; 0x216 216: 0f 92 push r0 218: cd b7 in r28, 0x3d ; 61 21a: de b7 in r29, 0x3e ; 62 21c: 8a 83 std Y+2, r24 ; 0x02 21e: 9b 83 std Y+3, r25 ; 0x03 bool twi_status = (twi->status & TWIM_STATUS_READY); 220: ea 81 ldd r30, Y+2 ; 0x02 222: fb 81 ldd r31, Y+3 ; 0x03 224: 82 89 ldd r24, Z+18 ; 0x12 226: 19 82 std Y+1, r1 ; 0x01 return twi_status; 228: 89 81 ldd r24, Y+1 ; 0x01 } 22a: 24 96 adiw r28, 0x04 ; 4 22c: cd bf out 0x3d, r28 ; 61 22e: de bf out 0x3e, r29 ; 62 230: cf 91 pop r28 232: df 91 pop r29 234: 08 95 ret 00000236 : */ bool TWI_MasterWrite(TWI_Master_t *twi, uint8_t address, uint8_t *writeData, uint8_t bytesToWrite) { 236: 0f 93 push r16 238: df 93 push r29 23a: cf 93 push r28 23c: cd b7 in r28, 0x3d ; 61 23e: de b7 in r29, 0x3e ; 62 240: 27 97 sbiw r28, 0x07 ; 7 242: cd bf out 0x3d, r28 ; 61 244: de bf out 0x3e, r29 ; 62 246: 8a 83 std Y+2, r24 ; 0x02 248: 9b 83 std Y+3, r25 ; 0x03 24a: 6c 83 std Y+4, r22 ; 0x04 24c: 4d 83 std Y+5, r20 ; 0x05 24e: 5e 83 std Y+6, r21 ; 0x06 250: 2f 83 std Y+7, r18 ; 0x07 bool twi_status = TWI_MasterWriteRead(twi, address, writeData, bytesToWrite, 0); 252: 8a 81 ldd r24, Y+2 ; 0x02 254: 9b 81 ldd r25, Y+3 ; 0x03 256: 2d 81 ldd r18, Y+5 ; 0x05 258: 3e 81 ldd r19, Y+6 ; 0x06 25a: 6c 81 ldd r22, Y+4 ; 0x04 25c: a9 01 movw r20, r18 25e: 2f 81 ldd r18, Y+7 ; 0x07 260: 00 e0 ldi r16, 0x00 ; 0 262: 0e 94 5a 01 call 0x2b4 ; 0x2b4 266: 89 83 std Y+1, r24 ; 0x01 return twi_status; 268: 89 81 ldd r24, Y+1 ; 0x01 } 26a: 27 96 adiw r28, 0x07 ; 7 26c: cd bf out 0x3d, r28 ; 61 26e: de bf out 0x3e, r29 ; 62 270: cf 91 pop r28 272: df 91 pop r29 274: 0f 91 pop r16 276: 08 95 ret 00000278 : * \retval false If transaction could not be started. */ bool TWI_MasterRead(TWI_Master_t *twi, uint8_t address, uint8_t bytesToRead) { 278: 0f 93 push r16 27a: df 93 push r29 27c: cf 93 push r28 27e: cd b7 in r28, 0x3d ; 61 280: de b7 in r29, 0x3e ; 62 282: 25 97 sbiw r28, 0x05 ; 5 284: cd bf out 0x3d, r28 ; 61 286: de bf out 0x3e, r29 ; 62 288: 8a 83 std Y+2, r24 ; 0x02 28a: 9b 83 std Y+3, r25 ; 0x03 28c: 6c 83 std Y+4, r22 ; 0x04 28e: 4d 83 std Y+5, r20 ; 0x05 bool twi_status = TWI_MasterWriteRead(twi, address, 0, 0, bytesToRead); 290: 8a 81 ldd r24, Y+2 ; 0x02 292: 9b 81 ldd r25, Y+3 ; 0x03 294: 6c 81 ldd r22, Y+4 ; 0x04 296: 40 e0 ldi r20, 0x00 ; 0 298: 50 e0 ldi r21, 0x00 ; 0 29a: 20 e0 ldi r18, 0x00 ; 0 29c: 0d 81 ldd r16, Y+5 ; 0x05 29e: 0e 94 5a 01 call 0x2b4 ; 0x2b4 2a2: 89 83 std Y+1, r24 ; 0x01 return twi_status; 2a4: 89 81 ldd r24, Y+1 ; 0x01 } 2a6: 25 96 adiw r28, 0x05 ; 5 2a8: cd bf out 0x3d, r28 ; 61 2aa: de bf out 0x3e, r29 ; 62 2ac: cf 91 pop r28 2ae: df 91 pop r29 2b0: 0f 91 pop r16 2b2: 08 95 ret 000002b4 : bool TWI_MasterWriteRead(TWI_Master_t *twi, uint8_t address, uint8_t *writeData, uint8_t bytesToWrite, uint8_t bytesToRead) { 2b4: 0f 93 push r16 2b6: df 93 push r29 2b8: cf 93 push r28 2ba: cd b7 in r28, 0x3d ; 61 2bc: de b7 in r29, 0x3e ; 62 2be: 2b 97 sbiw r28, 0x0b ; 11 2c0: cd bf out 0x3d, r28 ; 61 2c2: de bf out 0x3e, r29 ; 62 2c4: 8c 83 std Y+4, r24 ; 0x04 2c6: 9d 83 std Y+5, r25 ; 0x05 2c8: 6e 83 std Y+6, r22 ; 0x06 2ca: 4f 83 std Y+7, r20 ; 0x07 2cc: 58 87 std Y+8, r21 ; 0x08 2ce: 29 87 std Y+9, r18 ; 0x09 2d0: 0a 87 std Y+10, r16 ; 0x0a /*Parameter sanity check. */ if (bytesToWrite > TWIM_WRITE_BUFFER_SIZE) { 2d2: 89 85 ldd r24, Y+9 ; 0x09 2d4: 84 30 cpi r24, 0x04 ; 4 2d6: 10 f0 brcs .+4 ; 0x2dc return false; 2d8: 1b 86 std Y+11, r1 ; 0x0b 2da: 69 c0 rjmp .+210 ; 0x3ae } if (bytesToRead > TWIM_READ_BUFFER_SIZE) { 2dc: 8a 85 ldd r24, Y+10 ; 0x0a 2de: 89 30 cpi r24, 0x09 ; 9 2e0: 10 f0 brcs .+4 ; 0x2e6 return false; 2e2: 1b 86 std Y+11, r1 ; 0x0b 2e4: 64 c0 rjmp .+200 ; 0x3ae } /*Initiate transaction if bus is ready. */ if (twi->status == TWIM_STATUS_READY) { 2e6: ec 81 ldd r30, Y+4 ; 0x04 2e8: fd 81 ldd r31, Y+5 ; 0x05 2ea: 82 89 ldd r24, Z+18 ; 0x12 2ec: 88 23 and r24, r24 2ee: 09 f0 breq .+2 ; 0x2f2 2f0: 5d c0 rjmp .+186 ; 0x3ac twi->status = TWIM_STATUS_BUSY; 2f2: ec 81 ldd r30, Y+4 ; 0x04 2f4: fd 81 ldd r31, Y+5 ; 0x05 2f6: 81 e0 ldi r24, 0x01 ; 1 2f8: 82 8b std Z+18, r24 ; 0x12 twi->result = TWIM_RESULT_UNKNOWN; 2fa: ec 81 ldd r30, Y+4 ; 0x04 2fc: fd 81 ldd r31, Y+5 ; 0x05 2fe: 13 8a std Z+19, r1 ; 0x13 twi->address = address<<1; 300: 8e 81 ldd r24, Y+6 ; 0x06 302: 88 0f add r24, r24 304: ec 81 ldd r30, Y+4 ; 0x04 306: fd 81 ldd r31, Y+5 ; 0x05 308: 82 83 std Z+2, r24 ; 0x02 /* Fill write data buffer. */ uint8_t bufferIndex=0; 30a: 1b 82 std Y+3, r1 ; 0x03 for (bufferIndex=0; bufferIndex < bytesToWrite; bufferIndex++) { 30c: 1b 82 std Y+3, r1 ; 0x03 30e: 16 c0 rjmp .+44 ; 0x33c twi->writeData[bufferIndex] = writeData[bufferIndex]; 310: 8b 81 ldd r24, Y+3 ; 0x03 312: 48 2f mov r20, r24 314: 50 e0 ldi r21, 0x00 ; 0 316: 8b 81 ldd r24, Y+3 ; 0x03 318: 28 2f mov r18, r24 31a: 30 e0 ldi r19, 0x00 ; 0 31c: 8f 81 ldd r24, Y+7 ; 0x07 31e: 98 85 ldd r25, Y+8 ; 0x08 320: fc 01 movw r30, r24 322: e2 0f add r30, r18 324: f3 1f adc r31, r19 326: 20 81 ld r18, Z 328: 8c 81 ldd r24, Y+4 ; 0x04 32a: 9d 81 ldd r25, Y+5 ; 0x05 32c: 84 0f add r24, r20 32e: 95 1f adc r25, r21 330: fc 01 movw r30, r24 332: 33 96 adiw r30, 0x03 ; 3 334: 20 83 st Z, r18 twi->address = address<<1; /* Fill write data buffer. */ uint8_t bufferIndex=0; for (bufferIndex=0; bufferIndex < bytesToWrite; bufferIndex++) { 336: 8b 81 ldd r24, Y+3 ; 0x03 338: 8f 5f subi r24, 0xFF ; 255 33a: 8b 83 std Y+3, r24 ; 0x03 33c: 9b 81 ldd r25, Y+3 ; 0x03 33e: 89 85 ldd r24, Y+9 ; 0x09 340: 98 17 cp r25, r24 342: 30 f3 brcs .-52 ; 0x310 twi->writeData[bufferIndex] = writeData[bufferIndex]; } twi->bytesToWrite = bytesToWrite; 344: ec 81 ldd r30, Y+4 ; 0x04 346: fd 81 ldd r31, Y+5 ; 0x05 348: 89 85 ldd r24, Y+9 ; 0x09 34a: 86 87 std Z+14, r24 ; 0x0e twi->bytesToRead = bytesToRead; 34c: ec 81 ldd r30, Y+4 ; 0x04 34e: fd 81 ldd r31, Y+5 ; 0x05 350: 8a 85 ldd r24, Y+10 ; 0x0a 352: 87 87 std Z+15, r24 ; 0x0f twi->bytesWritten = 0; 354: ec 81 ldd r30, Y+4 ; 0x04 356: fd 81 ldd r31, Y+5 ; 0x05 358: 10 8a std Z+16, r1 ; 0x10 twi->bytesRead = 0; 35a: ec 81 ldd r30, Y+4 ; 0x04 35c: fd 81 ldd r31, Y+5 ; 0x05 35e: 11 8a std Z+17, r1 ; 0x11 /* If write command, send the START condition + Address + * 'R/_W = 0' */ if (twi->bytesToWrite > 0) { 360: ec 81 ldd r30, Y+4 ; 0x04 362: fd 81 ldd r31, Y+5 ; 0x05 364: 86 85 ldd r24, Z+14 ; 0x0e 366: 88 23 and r24, r24 368: 69 f0 breq .+26 ; 0x384 uint8_t writeAddress = twi->address & ~0x01; 36a: ec 81 ldd r30, Y+4 ; 0x04 36c: fd 81 ldd r31, Y+5 ; 0x05 36e: 82 81 ldd r24, Z+2 ; 0x02 370: 8e 7f andi r24, 0xFE ; 254 372: 8a 83 std Y+2, r24 ; 0x02 twi->interface->MASTER.ADDR = writeAddress; 374: ec 81 ldd r30, Y+4 ; 0x04 376: fd 81 ldd r31, Y+5 ; 0x05 378: 01 90 ld r0, Z+ 37a: f0 81 ld r31, Z 37c: e0 2d mov r30, r0 37e: 8a 81 ldd r24, Y+2 ; 0x02 380: 86 83 std Z+6, r24 ; 0x06 382: 11 c0 rjmp .+34 ; 0x3a6 } /* If read command, send the START condition + Address + * 'R/_W = 1' */ else if (twi->bytesToRead > 0) { 384: ec 81 ldd r30, Y+4 ; 0x04 386: fd 81 ldd r31, Y+5 ; 0x05 388: 87 85 ldd r24, Z+15 ; 0x0f 38a: 88 23 and r24, r24 38c: 61 f0 breq .+24 ; 0x3a6 uint8_t readAddress = twi->address | 0x01; 38e: ec 81 ldd r30, Y+4 ; 0x04 390: fd 81 ldd r31, Y+5 ; 0x05 392: 82 81 ldd r24, Z+2 ; 0x02 394: 81 60 ori r24, 0x01 ; 1 396: 89 83 std Y+1, r24 ; 0x01 twi->interface->MASTER.ADDR = readAddress; 398: ec 81 ldd r30, Y+4 ; 0x04 39a: fd 81 ldd r31, Y+5 ; 0x05 39c: 01 90 ld r0, Z+ 39e: f0 81 ld r31, Z 3a0: e0 2d mov r30, r0 3a2: 89 81 ldd r24, Y+1 ; 0x01 3a4: 86 83 std Z+6, r24 ; 0x06 } return true; 3a6: 81 e0 ldi r24, 0x01 ; 1 3a8: 8b 87 std Y+11, r24 ; 0x0b 3aa: 01 c0 rjmp .+2 ; 0x3ae } else { return false; 3ac: 1b 86 std Y+11, r1 ; 0x0b 3ae: 8b 85 ldd r24, Y+11 ; 0x0b } } 3b0: 2b 96 adiw r28, 0x0b ; 11 3b2: cd bf out 0x3d, r28 ; 61 3b4: de bf out 0x3e, r29 ; 62 3b6: cf 91 pop r28 3b8: df 91 pop r29 3ba: 0f 91 pop r16 3bc: 08 95 ret 000003be : * Check current status and calls the appropriate handler. * * \param twi The TWI_Master_t struct instance. */ void TWI_MasterInterruptHandler(TWI_Master_t *twi) { 3be: df 93 push r29 3c0: cf 93 push r28 3c2: 00 d0 rcall .+0 ; 0x3c4 3c4: cd b7 in r28, 0x3d ; 61 3c6: de b7 in r29, 0x3e ; 62 3c8: 8a 83 std Y+2, r24 ; 0x02 3ca: 9b 83 std Y+3, r25 ; 0x03 uint8_t currentStatus = twi->interface->MASTER.STATUS; 3cc: ea 81 ldd r30, Y+2 ; 0x02 3ce: fb 81 ldd r31, Y+3 ; 0x03 3d0: 01 90 ld r0, Z+ 3d2: f0 81 ld r31, Z 3d4: e0 2d mov r30, r0 3d6: 84 81 ldd r24, Z+4 ; 0x04 3d8: 89 83 std Y+1, r24 ; 0x01 /* If arbitration lost or bus error. */ if ((currentStatus & TWI_MASTER_ARBLOST_bm) || 3da: 89 81 ldd r24, Y+1 ; 0x01 3dc: 88 2f mov r24, r24 3de: 90 e0 ldi r25, 0x00 ; 0 3e0: 88 70 andi r24, 0x08 ; 8 3e2: 90 70 andi r25, 0x00 ; 0 3e4: 00 97 sbiw r24, 0x00 ; 0 3e6: 39 f4 brne .+14 ; 0x3f6 3e8: 89 81 ldd r24, Y+1 ; 0x01 3ea: 88 2f mov r24, r24 3ec: 90 e0 ldi r25, 0x00 ; 0 3ee: 84 70 andi r24, 0x04 ; 4 3f0: 90 70 andi r25, 0x00 ; 0 3f2: 00 97 sbiw r24, 0x00 ; 0 3f4: 29 f0 breq .+10 ; 0x400 (currentStatus & TWI_MASTER_BUSERR_bm)) { TWI_MasterArbitrationLostBusErrorHandler(twi); 3f6: 8a 81 ldd r24, Y+2 ; 0x02 3f8: 9b 81 ldd r25, Y+3 ; 0x03 3fa: 0e 94 1f 02 call 0x43e ; 0x43e 3fe: 19 c0 rjmp .+50 ; 0x432 } /* If master write interrupt. */ else if (currentStatus & TWI_MASTER_WIF_bm) { 400: 89 81 ldd r24, Y+1 ; 0x01 402: 88 2f mov r24, r24 404: 90 e0 ldi r25, 0x00 ; 0 406: 80 74 andi r24, 0x40 ; 64 408: 90 70 andi r25, 0x00 ; 0 40a: 00 97 sbiw r24, 0x00 ; 0 40c: 29 f0 breq .+10 ; 0x418 TWI_MasterWriteHandler(twi); 40e: 8a 81 ldd r24, Y+2 ; 0x02 410: 9b 81 ldd r25, Y+3 ; 0x03 412: 0e 94 4e 02 call 0x49c ; 0x49c 416: 0d c0 rjmp .+26 ; 0x432 } /* If master read interrupt. */ else if (currentStatus & TWI_MASTER_RIF_bm) { 418: 89 81 ldd r24, Y+1 ; 0x01 41a: 88 23 and r24, r24 41c: 2c f4 brge .+10 ; 0x428 TWI_MasterReadHandler(twi); 41e: 8a 81 ldd r24, Y+2 ; 0x02 420: 9b 81 ldd r25, Y+3 ; 0x03 422: 0e 94 c0 02 call 0x580 ; 0x580 426: 05 c0 rjmp .+10 ; 0x432 } /* If unexpected state. */ else { TWI_MasterTransactionFinished(twi, TWIM_RESULT_FAIL); 428: 8a 81 ldd r24, Y+2 ; 0x02 42a: 9b 81 ldd r25, Y+3 ; 0x03 42c: 66 e0 ldi r22, 0x06 ; 6 42e: 0e 94 19 03 call 0x632 ; 0x632 } } 432: 23 96 adiw r28, 0x03 ; 3 434: cd bf out 0x3d, r28 ; 61 436: de bf out 0x3e, r29 ; 62 438: cf 91 pop r28 43a: df 91 pop r29 43c: 08 95 ret 0000043e : * Handles TWI responses to lost arbitration and bus error. * * \param twi The TWI_Master_t struct instance. */ void TWI_MasterArbitrationLostBusErrorHandler(TWI_Master_t *twi) { 43e: df 93 push r29 440: cf 93 push r28 442: 00 d0 rcall .+0 ; 0x444 444: cd b7 in r28, 0x3d ; 61 446: de b7 in r29, 0x3e ; 62 448: 8a 83 std Y+2, r24 ; 0x02 44a: 9b 83 std Y+3, r25 ; 0x03 uint8_t currentStatus = twi->interface->MASTER.STATUS; 44c: ea 81 ldd r30, Y+2 ; 0x02 44e: fb 81 ldd r31, Y+3 ; 0x03 450: 01 90 ld r0, Z+ 452: f0 81 ld r31, Z 454: e0 2d mov r30, r0 456: 84 81 ldd r24, Z+4 ; 0x04 458: 89 83 std Y+1, r24 ; 0x01 /* If bus error. */ if (currentStatus & TWI_MASTER_BUSERR_bm) { 45a: 89 81 ldd r24, Y+1 ; 0x01 45c: 88 2f mov r24, r24 45e: 90 e0 ldi r25, 0x00 ; 0 460: 84 70 andi r24, 0x04 ; 4 462: 90 70 andi r25, 0x00 ; 0 464: 00 97 sbiw r24, 0x00 ; 0 466: 29 f0 breq .+10 ; 0x472 twi->result = TWIM_RESULT_BUS_ERROR; 468: ea 81 ldd r30, Y+2 ; 0x02 46a: fb 81 ldd r31, Y+3 ; 0x03 46c: 84 e0 ldi r24, 0x04 ; 4 46e: 83 8b std Z+19, r24 ; 0x13 470: 04 c0 rjmp .+8 ; 0x47a } /* If arbitration lost. */ else { twi->result = TWIM_RESULT_ARBITRATION_LOST; 472: ea 81 ldd r30, Y+2 ; 0x02 474: fb 81 ldd r31, Y+3 ; 0x03 476: 83 e0 ldi r24, 0x03 ; 3 478: 83 8b std Z+19, r24 ; 0x13 } /* Clear interrupt flag. */ twi->interface->MASTER.STATUS = currentStatus | TWI_MASTER_ARBLOST_bm; 47a: ea 81 ldd r30, Y+2 ; 0x02 47c: fb 81 ldd r31, Y+3 ; 0x03 47e: 01 90 ld r0, Z+ 480: f0 81 ld r31, Z 482: e0 2d mov r30, r0 484: 89 81 ldd r24, Y+1 ; 0x01 486: 88 60 ori r24, 0x08 ; 8 488: 84 83 std Z+4, r24 ; 0x04 twi->status = TWIM_STATUS_READY; 48a: ea 81 ldd r30, Y+2 ; 0x02 48c: fb 81 ldd r31, Y+3 ; 0x03 48e: 12 8a std Z+18, r1 ; 0x12 } 490: 23 96 adiw r28, 0x03 ; 3 492: cd bf out 0x3d, r28 ; 61 494: de bf out 0x3e, r29 ; 62 496: cf 91 pop r28 498: df 91 pop r29 49a: 08 95 ret 0000049c : * Handles TWI transactions (master write) and responses to (N)ACK. * * \param twi The TWI_Master_t struct instance. */ void TWI_MasterWriteHandler(TWI_Master_t *twi) { 49c: df 93 push r29 49e: cf 93 push r28 4a0: 00 d0 rcall .+0 ; 0x4a2 4a2: 00 d0 rcall .+0 ; 0x4a4 4a4: cd b7 in r28, 0x3d ; 61 4a6: de b7 in r29, 0x3e ; 62 4a8: 8d 83 std Y+5, r24 ; 0x05 4aa: 9e 83 std Y+6, r25 ; 0x06 /* Local variables used in if tests to avoid compiler warning. */ uint8_t bytesToWrite = twi->bytesToWrite; 4ac: ed 81 ldd r30, Y+5 ; 0x05 4ae: fe 81 ldd r31, Y+6 ; 0x06 4b0: 86 85 ldd r24, Z+14 ; 0x0e 4b2: 8c 83 std Y+4, r24 ; 0x04 uint8_t bytesToRead = twi->bytesToRead; 4b4: ed 81 ldd r30, Y+5 ; 0x05 4b6: fe 81 ldd r31, Y+6 ; 0x06 4b8: 87 85 ldd r24, Z+15 ; 0x0f 4ba: 8b 83 std Y+3, r24 ; 0x03 /* If NOT acknowledged (NACK) by slave cancel the transaction. */ if (twi->interface->MASTER.STATUS & TWI_MASTER_RXACK_bm) { 4bc: ed 81 ldd r30, Y+5 ; 0x05 4be: fe 81 ldd r31, Y+6 ; 0x06 4c0: 01 90 ld r0, Z+ 4c2: f0 81 ld r31, Z 4c4: e0 2d mov r30, r0 4c6: 84 81 ldd r24, Z+4 ; 0x04 4c8: 88 2f mov r24, r24 4ca: 90 e0 ldi r25, 0x00 ; 0 4cc: 80 71 andi r24, 0x10 ; 16 4ce: 90 70 andi r25, 0x00 ; 0 4d0: 00 97 sbiw r24, 0x00 ; 0 4d2: 79 f0 breq .+30 ; 0x4f2 twi->interface->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc; 4d4: ed 81 ldd r30, Y+5 ; 0x05 4d6: fe 81 ldd r31, Y+6 ; 0x06 4d8: 01 90 ld r0, Z+ 4da: f0 81 ld r31, Z 4dc: e0 2d mov r30, r0 4de: 83 e0 ldi r24, 0x03 ; 3 4e0: 83 83 std Z+3, r24 ; 0x03 twi->result = TWIM_RESULT_NACK_RECEIVED; 4e2: ed 81 ldd r30, Y+5 ; 0x05 4e4: fe 81 ldd r31, Y+6 ; 0x06 4e6: 85 e0 ldi r24, 0x05 ; 5 4e8: 83 8b std Z+19, r24 ; 0x13 twi->status = TWIM_STATUS_READY; 4ea: ed 81 ldd r30, Y+5 ; 0x05 4ec: fe 81 ldd r31, Y+6 ; 0x06 4ee: 12 8a std Z+18, r1 ; 0x12 4f0: 41 c0 rjmp .+130 ; 0x574 } /* If more bytes to write, send data. */ else if (twi->bytesWritten < bytesToWrite) { 4f2: ed 81 ldd r30, Y+5 ; 0x05 4f4: fe 81 ldd r31, Y+6 ; 0x06 4f6: 90 89 ldd r25, Z+16 ; 0x10 4f8: 8c 81 ldd r24, Y+4 ; 0x04 4fa: 98 17 cp r25, r24 4fc: e0 f4 brcc .+56 ; 0x536 uint8_t data = twi->writeData[twi->bytesWritten]; 4fe: ed 81 ldd r30, Y+5 ; 0x05 500: fe 81 ldd r31, Y+6 ; 0x06 502: 80 89 ldd r24, Z+16 ; 0x10 504: 28 2f mov r18, r24 506: 30 e0 ldi r19, 0x00 ; 0 508: 8d 81 ldd r24, Y+5 ; 0x05 50a: 9e 81 ldd r25, Y+6 ; 0x06 50c: 82 0f add r24, r18 50e: 93 1f adc r25, r19 510: fc 01 movw r30, r24 512: 33 96 adiw r30, 0x03 ; 3 514: 80 81 ld r24, Z 516: 8a 83 std Y+2, r24 ; 0x02 twi->interface->MASTER.DATA = data; 518: ed 81 ldd r30, Y+5 ; 0x05 51a: fe 81 ldd r31, Y+6 ; 0x06 51c: 01 90 ld r0, Z+ 51e: f0 81 ld r31, Z 520: e0 2d mov r30, r0 522: 8a 81 ldd r24, Y+2 ; 0x02 524: 87 83 std Z+7, r24 ; 0x07 ++twi->bytesWritten; 526: ed 81 ldd r30, Y+5 ; 0x05 528: fe 81 ldd r31, Y+6 ; 0x06 52a: 80 89 ldd r24, Z+16 ; 0x10 52c: 8f 5f subi r24, 0xFF ; 255 52e: ed 81 ldd r30, Y+5 ; 0x05 530: fe 81 ldd r31, Y+6 ; 0x06 532: 80 8b std Z+16, r24 ; 0x10 534: 1f c0 rjmp .+62 ; 0x574 } /* If bytes to read, send repeated START condition + Address + * 'R/_W = 1' */ else if (twi->bytesRead < bytesToRead) { 536: ed 81 ldd r30, Y+5 ; 0x05 538: fe 81 ldd r31, Y+6 ; 0x06 53a: 91 89 ldd r25, Z+17 ; 0x11 53c: 8b 81 ldd r24, Y+3 ; 0x03 53e: 98 17 cp r25, r24 540: 68 f4 brcc .+26 ; 0x55c uint8_t readAddress = twi->address | 0x01; 542: ed 81 ldd r30, Y+5 ; 0x05 544: fe 81 ldd r31, Y+6 ; 0x06 546: 82 81 ldd r24, Z+2 ; 0x02 548: 81 60 ori r24, 0x01 ; 1 54a: 89 83 std Y+1, r24 ; 0x01 twi->interface->MASTER.ADDR = readAddress; 54c: ed 81 ldd r30, Y+5 ; 0x05 54e: fe 81 ldd r31, Y+6 ; 0x06 550: 01 90 ld r0, Z+ 552: f0 81 ld r31, Z 554: e0 2d mov r30, r0 556: 89 81 ldd r24, Y+1 ; 0x01 558: 86 83 std Z+6, r24 ; 0x06 55a: 0c c0 rjmp .+24 ; 0x574 } /* If transaction finished, send STOP condition and set RESULT OK. */ else { twi->interface->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc; 55c: ed 81 ldd r30, Y+5 ; 0x05 55e: fe 81 ldd r31, Y+6 ; 0x06 560: 01 90 ld r0, Z+ 562: f0 81 ld r31, Z 564: e0 2d mov r30, r0 566: 83 e0 ldi r24, 0x03 ; 3 568: 83 83 std Z+3, r24 ; 0x03 TWI_MasterTransactionFinished(twi, TWIM_RESULT_OK); 56a: 8d 81 ldd r24, Y+5 ; 0x05 56c: 9e 81 ldd r25, Y+6 ; 0x06 56e: 61 e0 ldi r22, 0x01 ; 1 570: 0e 94 19 03 call 0x632 ; 0x632 } } 574: 26 96 adiw r28, 0x06 ; 6 576: cd bf out 0x3d, r28 ; 61 578: de bf out 0x3e, r29 ; 62 57a: cf 91 pop r28 57c: df 91 pop r29 57e: 08 95 ret 00000580 : * reading bytes from the TWI slave. * * \param twi The TWI_Master_t struct instance. */ void TWI_MasterReadHandler(TWI_Master_t *twi) { 580: df 93 push r29 582: cf 93 push r28 584: 00 d0 rcall .+0 ; 0x586 586: 0f 92 push r0 588: cd b7 in r28, 0x3d ; 61 58a: de b7 in r29, 0x3e ; 62 58c: 8b 83 std Y+3, r24 ; 0x03 58e: 9c 83 std Y+4, r25 ; 0x04 /* Fetch data if bytes to be read. */ if (twi->bytesRead < TWIM_READ_BUFFER_SIZE) { 590: eb 81 ldd r30, Y+3 ; 0x03 592: fc 81 ldd r31, Y+4 ; 0x04 594: 81 89 ldd r24, Z+17 ; 0x11 596: 88 30 cpi r24, 0x08 ; 8 598: e0 f4 brcc .+56 ; 0x5d2 uint8_t data = twi->interface->MASTER.DATA; 59a: eb 81 ldd r30, Y+3 ; 0x03 59c: fc 81 ldd r31, Y+4 ; 0x04 59e: 01 90 ld r0, Z+ 5a0: f0 81 ld r31, Z 5a2: e0 2d mov r30, r0 5a4: 87 81 ldd r24, Z+7 ; 0x07 5a6: 89 83 std Y+1, r24 ; 0x01 twi->readData[twi->bytesRead] = data; 5a8: eb 81 ldd r30, Y+3 ; 0x03 5aa: fc 81 ldd r31, Y+4 ; 0x04 5ac: 81 89 ldd r24, Z+17 ; 0x11 5ae: 28 2f mov r18, r24 5b0: 30 e0 ldi r19, 0x00 ; 0 5b2: 8b 81 ldd r24, Y+3 ; 0x03 5b4: 9c 81 ldd r25, Y+4 ; 0x04 5b6: 82 0f add r24, r18 5b8: 93 1f adc r25, r19 5ba: fc 01 movw r30, r24 5bc: 36 96 adiw r30, 0x06 ; 6 5be: 89 81 ldd r24, Y+1 ; 0x01 5c0: 80 83 st Z, r24 twi->bytesRead++; 5c2: eb 81 ldd r30, Y+3 ; 0x03 5c4: fc 81 ldd r31, Y+4 ; 0x04 5c6: 81 89 ldd r24, Z+17 ; 0x11 5c8: 8f 5f subi r24, 0xFF ; 255 5ca: eb 81 ldd r30, Y+3 ; 0x03 5cc: fc 81 ldd r31, Y+4 ; 0x04 5ce: 81 8b std Z+17, r24 ; 0x11 5d0: 0c c0 rjmp .+24 ; 0x5ea } /* If buffer overflow, issue STOP and BUFFER_OVERFLOW condition. */ else { twi->interface->MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc; 5d2: eb 81 ldd r30, Y+3 ; 0x03 5d4: fc 81 ldd r31, Y+4 ; 0x04 5d6: 01 90 ld r0, Z+ 5d8: f0 81 ld r31, Z 5da: e0 2d mov r30, r0 5dc: 83 e0 ldi r24, 0x03 ; 3 5de: 83 83 std Z+3, r24 ; 0x03 TWI_MasterTransactionFinished(twi, TWIM_RESULT_BUFFER_OVERFLOW); 5e0: 8b 81 ldd r24, Y+3 ; 0x03 5e2: 9c 81 ldd r25, Y+4 ; 0x04 5e4: 62 e0 ldi r22, 0x02 ; 2 5e6: 0e 94 19 03 call 0x632 ; 0x632 } /* Local variable used in if test to avoid compiler warning. */ uint8_t bytesToRead = twi->bytesToRead; 5ea: eb 81 ldd r30, Y+3 ; 0x03 5ec: fc 81 ldd r31, Y+4 ; 0x04 5ee: 87 85 ldd r24, Z+15 ; 0x0f 5f0: 8a 83 std Y+2, r24 ; 0x02 /* If more bytes to read, issue ACK and start a byte read. */ if (twi->bytesRead < bytesToRead) { 5f2: eb 81 ldd r30, Y+3 ; 0x03 5f4: fc 81 ldd r31, Y+4 ; 0x04 5f6: 91 89 ldd r25, Z+17 ; 0x11 5f8: 8a 81 ldd r24, Y+2 ; 0x02 5fa: 98 17 cp r25, r24 5fc: 40 f4 brcc .+16 ; 0x60e twi->interface->MASTER.CTRLC = TWI_MASTER_CMD_RECVTRANS_gc; 5fe: eb 81 ldd r30, Y+3 ; 0x03 600: fc 81 ldd r31, Y+4 ; 0x04 602: 01 90 ld r0, Z+ 604: f0 81 ld r31, Z 606: e0 2d mov r30, r0 608: 82 e0 ldi r24, 0x02 ; 2 60a: 83 83 std Z+3, r24 ; 0x03 60c: 0c c0 rjmp .+24 ; 0x626 } /* If transaction finished, issue NACK and STOP condition. */ else { twi->interface->MASTER.CTRLC = TWI_MASTER_ACKACT_bm | 60e: eb 81 ldd r30, Y+3 ; 0x03 610: fc 81 ldd r31, Y+4 ; 0x04 612: 01 90 ld r0, Z+ 614: f0 81 ld r31, Z 616: e0 2d mov r30, r0 618: 87 e0 ldi r24, 0x07 ; 7 61a: 83 83 std Z+3, r24 ; 0x03 TWI_MASTER_CMD_STOP_gc; TWI_MasterTransactionFinished(twi, TWIM_RESULT_OK); 61c: 8b 81 ldd r24, Y+3 ; 0x03 61e: 9c 81 ldd r25, Y+4 ; 0x04 620: 61 e0 ldi r22, 0x01 ; 1 622: 0e 94 19 03 call 0x632 ; 0x632 } } 626: 24 96 adiw r28, 0x04 ; 4 628: cd bf out 0x3d, r28 ; 61 62a: de bf out 0x3e, r29 ; 62 62c: cf 91 pop r28 62e: df 91 pop r29 630: 08 95 ret 00000632 : * * \param twi The TWI_Master_t struct instance. * \param result The result of the operation. */ void TWI_MasterTransactionFinished(TWI_Master_t *twi, uint8_t result) { 632: df 93 push r29 634: cf 93 push r28 636: 00 d0 rcall .+0 ; 0x638 638: cd b7 in r28, 0x3d ; 61 63a: de b7 in r29, 0x3e ; 62 63c: 89 83 std Y+1, r24 ; 0x01 63e: 9a 83 std Y+2, r25 ; 0x02 640: 6b 83 std Y+3, r22 ; 0x03 twi->result = result; 642: e9 81 ldd r30, Y+1 ; 0x01 644: fa 81 ldd r31, Y+2 ; 0x02 646: 8b 81 ldd r24, Y+3 ; 0x03 648: 83 8b std Z+19, r24 ; 0x13 twi->status = TWIM_STATUS_READY; 64a: e9 81 ldd r30, Y+1 ; 0x01 64c: fa 81 ldd r31, Y+2 ; 0x02 64e: 12 8a std Z+18, r1 ; 0x12 } 650: 23 96 adiw r28, 0x03 ; 3 652: cd bf out 0x3d, r28 ; 61 654: de bf out 0x3e, r29 ; 62 656: cf 91 pop r28 658: df 91 pop r29 65a: 08 95 ret