| FlipFlop Project Status (12/16/2009 - 17:17:52) | |||
| Project File: | FlipFlop.ise | Implementation State: | Placed and Routed |
| Module Name: | TopSheet |
|
No Errors |
| Target Device: | xc3s400-4tq144 |
|
1 Warning |
| Product Version: | ISE 11.1 |
|
All Signals Completely Routed |
| Design Goal: | Balanced |
|
All Constraints Met |
| Design Strategy: | Xilinx Default (unlocked) |
|
0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slices containing only related logic | 0 | 0 | 0% | ||
| Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
| Number of bonded IOBs | 3 | 97 | 3% | ||
| IOB Flip Flops | 1 | ||||
| Number of BUFGMUXs | 1 | 8 | 12% | ||
| Average Fanout of Non-Clock Nets | 1.00 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Mi 16. Dez 17:17:42 2009 | 0 | 0 | 0 | |
| Translation Report | Current | Mi 16. Dez 17:17:45 2009 | 0 | 1 Warning | 0 | |
| Map Report | Current | Mi 16. Dez 17:17:47 2009 | 0 | 0 | 2 Infos | |
| Place and Route Report | Current | Mi 16. Dez 17:17:50 2009 | 0 | 0 | 1 Info | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Mi 16. Dez 17:17:52 2009 | 0 | 0 | 2 Infos | |
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |