;*************************************************************************** ;* ;* "div24u" - 24/24 Bit Unsigned Division ;* ;* This subroutine divides the two 24-bit numbers ;* "ddu0:ddu1:ddu2" (dividend) and "dvu0:dvu1:dvu2" (divisor). ;* The result is placed in "dresu0:dresu1:dresu2" and the remainder in ;* "dremu0:dremu1:dremu2". ;* ;* Number of words :23 ;* Number of cycles :429/446 (Min/Max) ;* Low registers used :3 (dremu0,dremu1,dremu2) ;* High registers used :5 (dresu0/ddu0,dresu1/ddu1,dresu2/ddu2,dvu0,dvu1, ;* dvu2,dcntu) ;* ;*************************************************************************** ;***** Subroutine Register Variables .def drem24u0=r15 .def drem24u1=r14 .def drem24u2=r13 .def dres24u0=r16 .def dres24u1=r17 .def dres24u2=r18 .def dd24u0 =r16 .def dd24u1 =r17 .def dd24u2 =r18 .def dv24u0 =r19 .def dv24u1 =r20 .def dv24u2 =r21 .def dcnt24u =r22 ;***** Code div24u: clr drem24u0 ;clear remainder Low byte clr drem24u1 ;clear remainder Low byte sub drem24u2,drem24u2 ;clear remainder High byte and carry ldi dcnt24u,25 ;init loop counter d24u_1: rol dd24u0 ;shift left dividend rol dd24u1 rol dd24u2 dec dcnt24u ;decrement counter breq d24u_2 ;if done rol drem24u0 ;shift dividend into remainder rol drem24u1 rol drem24u2 sub drem24u0,dv24u0 ;remainder = remainder - divisor sbc drem24u1,dv24u1 sbc drem24u2,dv24u2 brcc d24u_3 ;if result negative add drem24u0,dv24u0 ;restore remainder adc drem24u1,dv24u1 adc drem24u2,dv24u2 clc ;clear carry to be shifted into result rjmp d24u_1 ;else d24u_2: ret ;return d24u_3: sec ;set carry to be shifted into result rjmp d24u_1