---------------------------------------------------------- -- Engineer: Lothar Miller -- -- Create Date: 18:00:29 12/27/2009 -- Design Name: -- Module Name: NEC_Decoder - Behavioral ---------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity NEC_Decoder is Port ( clk : in STD_LOGIC; NEC : in STD_LOGIC; Repeated : out STD_LOGIC; RXdata : out STD_LOGIC_VECTOR (7 downto 0)); end NEC_Decoder; architecture Behavioral of NEC_Decoder is constant oscclk : integer := 50000000; -- 50MHz z.B. FPGA signal necin : std_logic := '0'; signal necsr : std_logic_vector (1 downto 0) := (others=>'0'); constant timeout : integer := (oscclk/(1000000/20000))-1; -- Timeout: 20 ms, nach Timeout werden Daten übernommen. constant synclen : integer := (oscclk/(1000000/7000))-1; -- Sync-Pulse = 9ms constant rptlen : integer := (oscclk/(1000000/3000))-1; -- Repeat-Pulse: 2,25ms=Repeat / 4,5ms=Neu constant one : integer := (oscclk/(1000000/1685))-1; -- (2,25ms + 1,12ms)/2 signal cnt : integer range 0 to timeout := 0; signal bits : std_logic_vector (16 downto 0) := (0=>'1', others=>'0'); signal nextbit : std_logic := '0'; type necstates is (idle, sync, repeat, rx, latch); signal state : necstates := idle; begin -- Signalkonditionierung, nicht nötig, wenn NEC-Signal steilflankig process variable insr : std_logic_vector (31 downto 0) := (others=>'0'); begin wait until rising_edge(clk); insr := insr(insr'left-1 downto 0) & not NEC; if (insr=(insr'range=>'0')) then necin<='0'; end if; if (insr=(insr'range=>'1')) then necin<='1'; end if; end process; -- NEC-Decoder process begin wait until rising_edge(clk); necsr <= necsr(necsr'left-1 downto 0) & necin; if (cnt cnt <= 0; if (necsr = "11") then -- warten auf 1 --> Sync state <= sync; end if; when sync => if (necsr = "00") then -- warten auf 0 --> Repeat? cnt <= 0; if (cnt>synclen) then state <= repeat; else state <= idle; end if; end if; when repeat => if (necsr = "11") then -- warten auf 1 --> erstes Bit cnt <= 0; if (cnt>rptlen) then -- Neue Übertragung state <= rx; bits <= (0=>'1', others=>'0'); else Repeated <= '1'; -- wiederholte Übertragung state <= idle; end if; end if; when rx => if (necsr="01") then -- steigende Flanke cnt <= 0; bits <= bits(15 downto 0) & nextbit; end if; if (cnt=timeout) then -- Timeout --> Reset state <= idle; end if; if (bits(16)='1') then -- 16 Bits empfangen? state <= latch; end if; when latch => state <= idle; RXdata <= bits(RXdata'range); end case; end process; nextbit <= '1' when (cnt >= one) else '0'; end Behavioral;