library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port ( -- Clock video_clk : in std_logic; -- 27 MHz -- Video Ports hsync : in std_logic; vsync : in std_logic; -- Out Ports pixel_count : out std_logic_vector(10 downto 0) ); end counter; architecture a_counter of counter is -- Counter signal pcount : std_logic_vector(10 downto 0) := "00000000000"; -- Status signal pstate : std_logic := '0'; begin gw_extraction: process(hsync, video_clk) is -- variable p_c : std_logic_vector(10 downto 0); begin if(hsync = '0') then pstate <= '1'; pixel_count <= pcount; elsif(rising_edge(video_clk)) then if vsync = '0' then if pstate = '1' then -- damit im ersten takt auch 1 steht! pcount <= "00000000001"; -- für den nächsten hsync pstate <= '0'; else -- clock_counter pcount <= pcount + 1; end if; end if; end if; -- Kombinatorik end process; end a_counter;