---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:43:54 01/18/2010 -- Design Name: -- Module Name: pwm - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity pwm is generic(width: positive := 8); Port ( clock : in STD_LOGIC :='0'; value : in STD_LOGIC_VECTOR (63 downto 0):="0110011100011100011100001111010101000111010101011100001111000111"; en : in STD_LOGIC; oc1 : out STD_LOGIC; oc2 : out STD_LOGIC; oc3 : out STD_LOGIC; oc4 : out STD_LOGIC); end pwm; architecture Behavioral of pwm is component prescaler Port ( clock : in STD_LOGIC; clock_out : out STD_LOGIC); end component; component pwm_sub Port ( clock_in : in STD_LOGIC; value_in : in STD_LOGIC_VECTOR (15 downto 0); counter_in : in STD_LOGIC_VECTOR (15 downto 0); en : in STD_LOGIC; oc : out STD_LOGIC); end component; signal cnt : std_logic_vector(15 downto 0) :="0000000000000000";--(others=>:0); signal clock_sig : std_logic ; begin prescale1 : prescaler port map(clock => clock, -- component => entity i/o clock_out=> clock_sig); pwm1 : pwm_sub port map( clock_in => clock, value_in => value(15 downto 0), counter_in => cnt, en => en, oc => oc1); pwm2 : pwm_sub port map( clock_in => clock, value_in => value(31 downto 16), counter_in => cnt, en => en, oc => oc2); pwm3 : pwm_sub port map( clock_in => clock, value_in => value(47 downto 32), counter_in => cnt, en => en, oc => oc3); pwm4 : pwm_sub port map( clock_in => clock, value_in => value(63 downto 48), counter_in => cnt, en => en, oc => oc4); process(clock_sig) begin if rising_edge(clock_sig) then cnt <= cnt +1; end if; end process; end Behavioral;