---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:33:12 01/19/2010 -- Design Name: -- Module Name: spi - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity spi is generic( number_led : positive :=9; width: positive := 9*3); Port ( clock : in std_logic; en : in std_logic; data_in : in STD_LOGIC; sck : in STD_LOGIC; reset : in std_logic; data_out : out STD_LOGIC_VECTOR ((16*width)-1 downto 0)); end spi; architecture Behavioral of spi is signal data : STD_LOGIC_VECTOR ((16*width)-1 downto 0):="0000000000000000000000000000000000000000000000000000000000000000"; signal counter : integer range 0 to width-1; signal reset_sync : std_logic_vector (1 downto 0):="00"; signal sck_sync : std_logic_vector(2 downto 0) :="000"; signal en_sync : std_logic_vector(2 downto 0) :="000"; begin -- daten einlesen process (sck) begin if rising_edge(sck)then if (reset='1') then if(en = '0')then data <= data(data'left-1 downto 0) & data_in; end if; end if; end if; end process; process (en , reset) variable res: std_logic :='0'; begin if rising_edge(en) then counter <= counter +1; if (counter = number_led-1) then data_out<= data; res := '1'; end if; end if; if(reset='0') or (res='1')then counter <= 0; res :='0'; end if; end process; end Behavioral;