Release 10.1.03 - xst K.39 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to C:/ise10_proj/15fer10/test2/xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.11 secs --> Parameter xsthdpdir set to C:/ise10_proj/15fer10/test2/xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.11 secs --> Reading design: Modulator.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "Modulator.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "Modulator" Output Format : NGC Target Device : xc3s700a-4-fg484 ---- Source Options Top Module Name : Modulator Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : auto Automatic Register Balancing : Yes ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 24 Register Duplication : YES Move First FlipFlop Stage : YES Move Last FlipFlop Stage : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : true Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 2 Library Search Order : Modulator.lso Keep Hierarchy : NO Netlist Hierarchy : as_optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/ise10_proj/15fer10/test/Modulator.vhd" in Library work. Architecture behavioral of Entity modulator is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ) with generics. cntWidth = 14 ========================================================================= * HDL Analysis * ========================================================================= Analyzing generic Entity in library (Architecture ). cntWidth = 14 Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "C:/ise10_proj/15fer10/test/Modulator.vhd". WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1306 - Output is never assigned. WARNING:Xst:1306 - Output is never assigned. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. Found 14-bit updown counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 14-bit adder carry out for signal created at line 81. Found 14-bit comparator greatequal for signal created at line 67. Found 15-bit comparator greatequal for signal created at line 81. Found 14-bit register for signal . Summary: inferred 1 Counter(s). inferred 16 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 2 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 14-bit adder carry out : 1 # Counters : 1 14-bit updown counter : 1 # Registers : 3 1-bit register : 2 14-bit register : 1 # Comparators : 2 14-bit comparator greatequal : 1 15-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Loading device for application Rf_Device from file '3s700a.nph' in environment C:\Programme\Xilinx\10.1\ISE. ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Adders/Subtractors : 1 14-bit adder carry out : 1 # Counters : 1 14-bit updown counter : 1 # Registers : 16 Flip-Flops : 16 # Comparators : 2 14-bit comparator greatequal : 1 15-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block Modulator, actual ratio is 0. Replicating register cntDwn to handle IOB=TRUE attribute Replicating register Ph_tmp to handle IOB=TRUE attribute Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 32 Flip-Flops : 32 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : Modulator.ngr Top Level Output File Name : Modulator Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 56 Cell Usage : # BELS : 157 # GND : 1 # INV : 4 # LUT1 : 13 # LUT2 : 43 # LUT3 : 3 # LUT4 : 6 # LUT4_L : 2 # MUXCY : 56 # VCC : 1 # XORCY : 28 # FlipFlops/Latches : 32 # FD : 16 # FDE : 16 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 17 # IBUF : 14 # OBUF : 3 ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s700afg484-4 Number of Slices: 36 out of 5888 0% Number of Slice Flip Flops: 16 out of 11776 0% Number of 4 input LUTs: 71 out of 11776 0% Number of IOs: 56 Number of bonded IOBs: 18 out of 372 4% IOB Flip Flops: 16 Number of GCLKs: 1 out of 24 4% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 32 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: 7.416ns (Maximum Frequency: 134.844MHz) Minimum input arrival time before clock: 1.521ns Maximum output required time after clock: 6.599ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'clk' Clock period: 7.416ns (frequency: 134.844MHz) Total number of paths / destination ports: 967 / 34 ------------------------------------------------------------------------- Delay: 7.416ns (Levels of Logic = 18) Source: TQ14_tmp_1 (FF) Destination: Ph_tmp (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: TQ14_tmp_1 to Ph_tmp Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDE:C->Q 2 0.591 0.590 TQ14_tmp_1 (TQ14_tmp_1) LUT1:I0->O 1 0.648 0.000 Madd_Ph_tmp_addsub0001_cy<1>_rt (Madd_Ph_tmp_addsub0001_cy<1>_rt) MUXCY:S->O 1 0.632 0.000 Madd_Ph_tmp_addsub0001_cy<1> (Madd_Ph_tmp_addsub0001_cy<1>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<2> (Madd_Ph_tmp_addsub0001_cy<2>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<3> (Madd_Ph_tmp_addsub0001_cy<3>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<4> (Madd_Ph_tmp_addsub0001_cy<4>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<5> (Madd_Ph_tmp_addsub0001_cy<5>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<6> (Madd_Ph_tmp_addsub0001_cy<6>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<7> (Madd_Ph_tmp_addsub0001_cy<7>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<8> (Madd_Ph_tmp_addsub0001_cy<8>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<9> (Madd_Ph_tmp_addsub0001_cy<9>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<10> (Madd_Ph_tmp_addsub0001_cy<10>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<11> (Madd_Ph_tmp_addsub0001_cy<11>) MUXCY:CI->O 1 0.065 0.000 Madd_Ph_tmp_addsub0001_cy<12> (Madd_Ph_tmp_addsub0001_cy<12>) XORCY:CI->O 1 0.844 0.500 Madd_Ph_tmp_addsub0001_xor<13> (Ph_tmp_addsub0001<13>) LUT2:I1->O 1 0.643 0.000 Mcompar_Ph_tmp_cmp_ge0001_lut<13> (Mcompar_Ph_tmp_cmp_ge0001_lut<13>) MUXCY:S->O 1 0.632 0.000 Mcompar_Ph_tmp_cmp_ge0001_cy<13> (Mcompar_Ph_tmp_cmp_ge0001_cy<13>) MUXCY:CI->O 1 0.269 0.452 Mcompar_Ph_tmp_cmp_ge0001_cy<14> (Ph_tmp_cmp_ge0001) LUT3:I2->O 2 0.648 0.000 Ph_tmp_mux00021 (Ph_tmp_mux0002) FD:D 0.252 Ph_tmp ---------------------------------------- Total 7.416ns (5.874ns logic, 1.542ns route) (79.2% logic, 20.8% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 14 / 14 ------------------------------------------------------------------------- Offset: 1.521ns (Levels of Logic = 1) Source: TQ14<0> (PAD) Destination: TQ14_tmp_0 (FF) Destination Clock: clk rising Data Path: TQ14<0> to TQ14_tmp_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.849 0.420 TQ14_0_IBUF (TQ14_0_IBUF) FDE:D 0.252 TQ14_tmp_0 ---------------------------------------- Total 1.521ns (1.101ns logic, 0.420ns route) (72.4% logic, 27.6% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 3 / 3 ------------------------------------------------------------------------- Offset: 6.599ns (Levels of Logic = 2) Source: Ph_tmp_1 (FF) Destination: Ph<0> (PAD) Source Clock: clk rising Data Path: Ph_tmp_1 to Ph<0> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FD:C->Q 1 0.591 0.420 Ph_tmp_1 (Ph_tmp_1) INV:I->O 1 0.648 0.420 Ph_0_not00001_INV_0 (Ph_0_OBUF) OBUF:I->O 4.520 Ph_0_OBUF (Ph<0>) ---------------------------------------- Total 6.599ns (5.759ns logic, 0.840ns route) (87.3% logic, 12.7% route) ========================================================================= Total REAL time to Xst completion: 5.00 secs Total CPU time to Xst completion: 5.03 secs --> Total memory usage is 149356 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 13 ( 0 filtered) Number of infos : 0 ( 0 filtered)