-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 08:16:39 02/16/2010 -- Design Name: -- Module Name: C:/Xilinx/Simulator/Simulator_Version01/MULTIPLIKATION_BENCH_2.vhd -- Project Name: Simulator_Version01 -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: Amplitude_Glukose_Multiplikation -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY MULTIPLIKATION_BENCH_2 IS END MULTIPLIKATION_BENCH_2; ARCHITECTURE behavior OF MULTIPLIKATION_BENCH_2 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Amplitude_Glukose_Multiplikation PORT( clk : IN std_logic; ce : IN std_logic; sclr : IN std_logic; bypass : IN std_logic; a : IN std_logic_vector(11 downto 0); b : IN std_logic_vector(11 downto 0); s : OUT std_logic_vector(23 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal ce : std_logic := '0'; signal sclr : std_logic := '0'; signal bypass : std_logic := '0'; signal a : std_logic_vector(11 downto 0) := (others => '0'); signal b : std_logic_vector(11 downto 0) := (others => '0'); --Outputs signal s : std_logic_vector(23 downto 0); -- Clock period definitions constant clk_period : time := 50000 ps; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Amplitude_Glukose_Multiplikation PORT MAP ( clk => clk, ce => ce, sclr => sclr, bypass => bypass, a => a, b => b, s => s ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin a <= "111111000000"; b <= "111111000000"; wait for 5000000 ns; a <= "111111001000"; b <= "111111001000"; wait for 7000000 ns; wait; end process; END;