---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:45:55 09/15/2009 -- Design Name: -- Module Name: sinnus - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; Entity sinnus is Port ( CLK : in std_logic; D_out1 : out std_logic_vector (7 downto 0); D_out2 : out std_logic_vector (7 downto 0); D_out3 : out std_logic_vector (7 downto 0); Freq_Data : in std_logic_vector (7 downto 0) ); end sinnus; Architecture RTL of sinnus is signal Result1 : std_logic_vector (7 downto 0); signal Result2 : std_logic_vector (7 downto 0); signal Result3 : std_logic_vector (7 downto 0); signal Accum1 : unsigned (25 downto 0) := (others=>'0'); signal Accum2 : unsigned (25 downto 0) := "01010101010101010101010101" ;--[(2^26)-1]/3 = 22.369.621 signal Accum3 : unsigned (25 downto 0) := "10101010101010101010101010"; --2[(2^26)-1]/3= 44.739.242 --signal Freq_Data : unsigned(7 downto 0) := x"43";-- 67 -- Takte = 2^26/Freq_Data -->fsinnus = fclk/Takte -- fsinnus = fclk*Freq_Data/2^26 -- fsinnus = 50 Hz-->Freq_Data = 67 -- fsinnus_min = circa 1 Hz(mit Freq_Data = 1); -- fsinnus_max = circa 189 Hz(mit Freq_Data =255); alias Address1 : unsigned (6 downto 0) is Accum1(Accum1'high-1 downto Accum1'high-7); alias Address2 : unsigned (6 downto 0) is Accum2(Accum2'high-1 downto Accum2'high-7); alias Address3 : unsigned (6 downto 0) is Accum3(Accum3'high-1 downto Accum3'high-7); alias Sign1 : std_logic is Accum1(Accum1'high); -- MSB alias Sign2 : std_logic is Accum2(Accum2'high); alias Sign3 : std_logic is Accum3(Accum3'high); signal Amplitude :integer :=0; begin process begin wait until rising_edge(CLK); Accum1 <= Accum1 + unsigned(Freq_Data); Accum2 <= Accum2 + unsigned(Freq_Data); Accum3 <= Accum3 + unsigned(Freq_Data); end process; process (Address1,Address2,Address3) type Rom128x8 is array (0 to 127) of std_logic_vector (7 downto 0); --Tabelleswerte von 0 nach pi constant Sinus_Rom : Rom128x8 := ( x"00", x"03", x"06", x"09", x"0c", x"0f", x"12", x"15", x"18", x"1b", x"1e", x"21", x"24", x"27", x"2a", x"2d", x"30", x"33", x"36", x"39", x"3b", x"3e", x"41", x"43", x"46", x"49", x"4b", x"4e", x"50", x"52", x"55", x"57", x"59", x"5b", x"5e", x"60", x"62", x"64", x"66", x"67", x"69", x"6b", x"6c", x"6e", x"70", x"71", x"72", x"74", x"75", x"76", x"77", x"78", x"79", x"7a", x"7b", x"7b", x"7c", x"7d", x"7d", x"7e", x"7e", x"7e", x"7e", x"7e", x"7f", x"7e", x"7e", x"7e", x"7e", x"7e", x"7d", x"7d", x"7c", x"7b", x"7b", x"7a", x"79", x"78", x"77", x"76", x"75", x"74", x"72", x"71", x"70", x"6e", x"6c", x"6b", x"69", x"67", x"66", x"64", x"62", x"60", x"5e", x"5b", x"59", x"57", x"55", x"52", x"50", x"4e", x"4b", x"49", x"46", x"43", x"41", x"3e", x"3b", x"39", x"36", x"33", x"30", x"2d", x"2a", x"27", x"24", x"21", x"1e", x"1b", x"18", x"15", x"12", x"0f", x"0c", x"09", x"06", x"03" ); begin Result1 <= Sinus_Rom (to_integer(Address1)); Result2 <= Sinus_Rom (to_integer(Address2)); Result3 <= Sinus_Rom (to_integer(Address3)); end process; -- Output registers process begin wait until rising_edge(CLK); --Von 0 to (maxAccum1)/2 : darstellen sinus im Bereich(0,pi) --Von (maxAccum1)/2 to maxAccum1) : darstellen sinus im Bereich(pi,2pi) --D_out1 <= Result1; if (Sign1='1') then for Amplitude in 0 to 25 loop D_out1 <= std_logic_vector(to_unsigned(127,8)+ unsigned(Result1)*Amplitude/128); end loop; else for Amplitude in 0 to 25 loop D_out1 <= std_logic_vector (to_unsigned(127,8)- unsigned(Result1)*Amplitude/128); end loop; end if; -- Sign2 und Sing3 wird nicht benutzt if (Sign2='1') then D_out2 <= std_logic_vector(to_unsigned(127,8)+ unsigned(Result2)); else D_out2 <= std_logic_vector (to_unsigned(127,8)- unsigned(Result2)); end if; if (Sign3='1') then D_out3 <= std_logic_vector(to_unsigned(127,8)+ unsigned(Result3)); else D_out3 <= std_logic_vector (to_unsigned(127,8)- unsigned(Result3)); end if; end process; end RTL;