---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 08:52:09 11/27/2009 -- Design Name: -- Module Name: adcamp01 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity adcamp01 is port( clk: in STD_LOGIC; reset: in STD_LOGIC; spi_sck: out STD_LOGIC; ad_conv: out STD_LOGIC; ad_conv2: out STD_LOGIC; spi_miso: in STD_LOGIC; spi_mosi : out STD_LOGIC; amp_cs : out STD_LOGIC; amp_shdn : out STD_LOGIC; amp_dout : in STD_LOGIC; switch : in STD_LOGIC_VECTOR (3 downto 0); led : out STD_LOGIC_VECTOR (7 downto 0); adcwerte: out STD_LOGIC_VECTOR(31 downto 0) := x"00000000"; --ausgang: out STD_LOGIC; abtasten: out STD_LOGIC; --disables spi_ss_b : out STD_LOGIC; dac_cs : out STD_LOGIC; sf_ce0: out STD_LOGIC; fpga_init_b: out STD_LOGIC ); end adcamp01; architecture Behavioral of adcamp01 is signal counter : STD_LOGIC_VECTOR(7 downto 0):= x"00"; --zählt manchmal mit langsameren geschwindigkeit signal daten : STD_LOGIC_VECTOR(31 downto 0):= x"00000000"; signal conv : STD_LOGIC; signal init: STD_LOGIC_VECTOR (7 downto 0) := x"11";--amplifier initialisierung signal x: STD_LOGIC:= '0'; signal ampli_led : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal adc_led : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal counter2 : STD_LOGIC_VECTOR(7 downto 0) := x"00"; signal counter3 : STD_LOGIC_VECTOR(7 downto 0) := x"00"; begin amp_shdn <= '0'; --spi_sck <= clk; --ausgang <= spi_miso; process(clk,reset) begin ------------------------------SWITCHES------------------ init(7) <= '0';--switch(3); init(3) <= '0';--switch(3); init(6) <= '0';--switch(2); init(2) <= '0';--switch(2); init(5) <= '0';--switch(1); init(1) <= '0';--switch(1); init(4) <= '1';--switch(0); init(0) <= '1';--switch(0); spi_ss_b <= '1'; dac_cs <= '1'; sf_ce0 <= '1'; fpga_init_b <= '1'; ---------------------------ENDSWITCHES------------------ if reset = '1' then -- reset counter <= x"00"; --ampli_led <= x"00"; --adc_led <= x"00"; elsif rising_edge(clk) then if(counter < x"73" ) then counter <= counter + x"01"; else if counter2 < x"03" then counter <= x"00"; counter2 <= counter2 + x"01"; else counter <= x"30"; end if; -- --counter2 <= x"01"; --if(x = '0') then --else counter <= x"00"; --end if; --x <= '1'; --if(switch(0) = '1') then --counter <= x"00"; --end if; end if; if switch(0) = '0' then led <= ampli_led; elsif switch(0) = '1' then led <= adc_led; end if; ----------------LED FÜR AMP------------------- case counter is WHEN x"05" => ampli_led(7) <= amp_dout; WHEN x"0B" => ampli_led(6) <= amp_dout; WHEN x"11" => ampli_led(5) <= amp_dout; WHEN x"17" => ampli_led(4) <= amp_dout; WHEN x"1D" => ampli_led(3) <= amp_dout; WHEN x"23" => ampli_led(2) <= amp_dout; WHEN x"29" => ampli_led(1) <= amp_dout; WHEN x"2F" => ampli_led(0) <= amp_dout; WHEN OTHERS => null; end case; ----------------LED FÜR AMP ENDE-------------- --if(counter2 < x"03") then --case counter is --when x"00" => spi_sck <= '0'; --when x"01" => spi_sck <= '0'; --when x"02" => spi_sck <= '0'; --when x"03" => spi_sck <= '1';--1 --when x"04" => spi_sck <= '1'; --when x"05" => spi_sck <= '1'; --when x"06" => spi_sck <= '0'; --when x"07" => spi_sck <= '0'; --when x"08" => spi_sck <= '0'; --when x"09" => spi_sck <= '1';--1 --when x"0A" => spi_sck <= '1'; --when x"0B" => spi_sck <= '1'; --when x"0C" => spi_sck <= '0'; --when x"0D" => spi_sck <= '0'; --when x"0E" => spi_sck <= '0'; --when x"0F" => spi_sck <= '1';--1 --when x"10" => spi_sck <= '1'; --when x"11" => spi_sck <= '1'; --when x"12" => spi_sck <= '0'; ---when x"13" => spi_sck <= '0'; --when x"14" => spi_sck <= '0'; --when x"15" => spi_sck <= '1';--1 --when x"16" => spi_sck <= '1'; --when x"17" => spi_sck <= '1'; --when x"18" => spi_sck <= '0'; --when x"19" => spi_sck <= '0'; --when x"1A" => spi_sck <= '0'; --when x"1B" => spi_sck <= '1';--1 ---when x"1C" => spi_sck <= '1'; --when x"1D" => spi_sck <= '1'; --when x"1E" => spi_sck <= '0'; --when x"1F" => spi_sck <= '0'; --when x"20" => spi_sck <= '0'; --when x"21" => spi_sck <= '1';--1 --when x"22" => spi_sck <= '1'; --when x"23" => spi_sck <= '1'; --when x"24" => spi_sck <= '0'; --when x"25" => spi_sck <= '0'; --when x"26" => spi_sck <= '0'; --when x"27" => spi_sck <= '1';--1 --when x"28" => spi_sck <= '1'; --when x"29" => spi_sck <= '1'; --when x"2A" => spi_sck <= '0'; --when x"2B" => spi_sck <= '0'; --when x"2C" => spi_sck <= '0'; ---when x"2D" => spi_sck <= '1';--1 --when x"2E" => spi_sck <= '1'; --when x"2F" => spi_sck <= '1'; --when others => spi_sck <= clk; --when others => null; --end case; --else spi_sck <= clk; --end if; end if; end process; process(clk) begin if falling_edge(clk) then if(counter3 < x"24") then if counter2 = x"03" then counter3 <= counter3 + x"01"; end if; else counter3 <= x"00"; end if; -----------------DATENAUSLESEN---------------- case counter3 is when x"04" => adc_led(7) <= spi_miso; when x"05" => adc_led(6) <= spi_miso; when x"06" => adc_led(5) <= spi_miso; when x"07" => adc_led(4) <= spi_miso; when x"08" => adc_led(3) <= spi_miso; when x"09" => adc_led(2) <= spi_miso; when x"0A" => adc_led(1) <= spi_miso; when x"0B" => adc_led(0) <= spi_miso; when x"0C" => adcwerte(5) <= spi_miso; when x"0D" => adcwerte(4) <= spi_miso; when x"0E" => adcwerte(3) <= spi_miso; when x"0F" => adcwerte(2) <= spi_miso; when x"10" => adcwerte(1) <= spi_miso; when x"11" => adcwerte(0) <= spi_miso; when x"14" => adcwerte(28) <= spi_miso; when x"15" => adcwerte(27) <= spi_miso; when x"16" => adcwerte(26) <= spi_miso; when x"17" => adcwerte(25) <= spi_miso; when x"18" => adcwerte(24) <= spi_miso; when x"19" => adcwerte(23) <= spi_miso; when x"1A" => adcwerte(22) <= spi_miso; --22 when x"1B" => adcwerte(21) <= spi_miso; --21 when x"1C" => adcwerte(20) <= spi_miso; --20 when x"1D" => adcwerte(19) <= spi_miso; --19 when x"1F" => adcwerte(18) <= spi_miso; --18 when x"20" => adcwerte(17) <= spi_miso; --17 when x"21" => adcwerte(16) <= spi_miso; --16 when x"22" => adcwerte(15) <= spi_miso; --15 when others => null; end case; -----------------DATENAUSLESEN ENDE----------- end if; end process; --with counter select --spi_sck <= --'1' when x"03",--1 --'1' when x"04", --'1' when x"05", --'1' when x"09",--1 --'1' when x"0A", --'1' when x"0B", --'1' when x"0F",--1 --'1' when x"10", --'1' when x"11", --'1' when x"15",--1 --'1' when x"16", --'1' when x"17", --'1' when x"1B",--1 --'1' when x"1C", --'1' when x"1D", --'1' when x"21",--1 --'1' when x"22", --'1' when x"23", --'1' when x"27",--1 --'1' when x"28", --'1' when x"29", --'1' when x"2D",--1 --'1' when x"2E", --'1' when x"2F", --'1' when x"31",--1 --adc beginnt --'1' when x"33", --'1' when x"35", --'1' when x"37", --'1' when x"39", --'1' when x"3B", --'1' when x"3D", --'1' when x"3F", --'1' when x"41", --'1' when x"43", --'1' when x"45", --'1' when x"47", --'1' when x"49", --'1' when x"4B", --'1' when x"4D", --'1' when x"4F", --'1' when x"51", --'1' when x"53", --'1' when x"55", --'1' when x"57", --'1' when x"59", --'1' when x"5B", --'1' when x"5D", --'1' when x"5F", --'1' when x"61", --'1' when x"63", --'1' when x"65", --'1' when x"67", --'1' when x"69", --'1' when x"6B", --'1' when x"6D", --'1' when x"6F", --'1' when x"71", --'1' when x"73", --'0' when others; ---------------------------------clk test----------- with counter select spi_sck <= '0' when x"00", '0' when x"01", '0' when x"02", '1' when x"03",--1 '1' when x"04", '1' when x"05", '0' when x"06", '0' when x"07", '0' when x"08", '1' when x"09",--1 '1' when x"0A", '1' when x"0B", '0' when x"0C", '0' when x"0D", '0' when x"0E", '1' when x"0F",--1 '1' when x"10", '1' when x"11", '0' when x"12", '0' when x"13", '0' when x"14", '1' when x"15",--1 '1' when x"16", '1' when x"17", '0' when x"18", '0' when x"19", '0' when x"1A", '1' when x"1B",--1 '1' when x"1C", '1' when x"1D", '0' when x"1E", '0' when x"1F", '0' when x"20", '1' when x"21",--1 '1' when x"22", '1' when x"23", '0' when x"24", '0' when x"25", '0' when x"26", '1' when x"27",--1 '1' when x"28", '1' when x"29", '0' when x"2A", '0' when x"2B", '0' when x"2C", '1' when x"2D",--1 '1' when x"2E", '1' when x"2F", clk when others; ---------------------------------clk test ende------ with counter select spi_mosi <= init(7) when x"00", init(7) when x"01", init(7) when x"02", init(7) when x"03", init(7) when x"04", init(7) when x"05", init(6) when x"06", init(6) when x"07", init(6) when x"08", init(6) when x"09", init(6) when x"0A", init(6) when x"0B", init(5) when x"0C", init(5) when x"0D", init(5) when x"0E", init(5) when x"0F", init(5) when x"10", init(5) when x"11", init(4) when x"12", init(4) when x"13", init(4) when x"14", init(4) when x"15", init(4) when x"16", init(4) when x"17", init(3) when x"18", init(3) when x"19", init(3) when x"1A", init(3) when x"1B", init(3) when x"1C", init(3) when x"1D", init(2) when x"1E", init(2) when x"1F", init(2) when x"20", init(2) when x"21", init(2) when x"22", init(2) when x"23", init(1) when x"24", init(1) when x"25", init(1) when x"26", init(1) when x"27", init(1) when x"28", init(1) when x"29", init(0) when x"2A", init(0) when x"2B", init(0) when x"2C", init(0) when x"2D", init(0) when x"2E", init(0) when x"2F", '0' when others; with counter3 select ad_conv <= '1' when x"01", '0' when others; --zum testen with counter3 select ad_conv2 <= '1' when x"01", '0' when others; --ende testen with counter select amp_cs <= '1' when x"00", '1' when x"01", '1' when x"2F", '1' when x"30", '1' when x"31", '1' when x"32", '1' when x"33", '1' when x"34", '1' when x"35", '1' when x"36", '1' when x"37", '1' when x"38", '1' when x"39", '1' when x"3A", '1' when x"3B", '1' when x"3C", '1' when x"3D", '1' when x"3E", '1' when x"3F", '1' when x"40", '1' when x"41", '1' when x"42", '1' when x"43", '1' when x"44", '1' when x"45", '1' when x"46", '1' when x"47", '1' when x"48", '1' when x"49", '1' when x"4A", '1' when x"4B", '1' when x"4C", '1' when x"4D", '1' when x"4E", '1' when x"4F", '1' when x"50", '1' when x"51", '1' when x"52", '1' when x"53", '1' when x"54", '1' when x"55", '1' when x"56", '1' when x"57", '1' when x"58", '1' when x"59", '1' when x"5A", '1' when x"5B", '1' when x"5C", '1' when x"5D", '1' when x"5E", '1' when x"5F", '1' when x"60", '1' when x"61", '1' when x"62", '1' when x"63", '1' when x"64", '1' when x"65", '1' when x"66", '1' when x"67", '1' when x"68", '1' when x"69", '1' when x"6A", '1' when x"6B", '1' when x"6C", '1' when x"6D", '1' when x"6E", '1' when x"6F", '1' when x"70", '1' when x"71", '1' when x"72", '1' when x"73", '0' when others; with counter select abtasten <= '1' when x"36", '1' when x"38", '1' when x"3A", '1' when x"3C", '1' when x"3E", '1' when x"40", '1' when x"42", '1' when x"44", '1' when x"46", '1' when x"48", '1' when x"4A", '1' when x"4C", '1' when x"4E", '1' when x"50", '1' when x"56", '1' when x"58", '1' when x"5A", '1' when x"5C", '1' when x"5E", '1' when x"60", '1' when x"62", '1' when x"64", '1' when x"66", '1' when x"68", '1' when x"6A", '1' when x"6C", '1' when x"6E", '1' when x"70", '0' when others; end Behavioral;