library ieee; use ieee.std_logic_1164.all; entity tb_upcount is end tb_upcount; architecture stim of tb_upcount is component upcount is port( resb : in std_logic; up : in std_logic; down : in std_logic; O : out std_logic_vector(3 downto 0) ); end component upcount; signal resb : std_logic := '0'; signal up : std_logic := '0'; signal down : std_logic := '0'; signal O : std_logic_vector(3 downto 0); begin up_count_i : upcount port map( resb => resb, up => up, down => down, O => O ); process begin wait for 1 us; resb <= '1'; wait for 1 us; for i in 0 to 10 loop up <= '1'; wait for 1 us; up <= '0'; wait for 1 us; end loop; wait for 5 us; for i in 0 to 9 loop down <= '1'; wait for 1 us; down <= '0'; wait for 1 us; end loop; wait for 5 us; for i in 0 to 20 loop up <= '1'; wait for 1 us; up <= '0'; wait for 1 us; end loop; wait for 5 us; for i in 0 to 20 loop down <= '1'; wait for 1 us; down <= '0'; wait for 1 us; end loop; wait for 5 us; for i in 0 to 20 loop up <= '1'; wait for 1 us; up <= '0'; wait for 1 us; end loop; wait; end process; end stim;