================================================================================ Timing constraint: COMP "DOUT0A_P" OFFSET = IN 3.015 ns VALID 3.125 ns BEFORE COMP "TCLK_P" "RISING"; 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 2.972ns. -------------------------------------------------------------------------------- Slack (setup path): 0.043ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: DOUT0A_P (PAD) Destination: A0_S2P_1laneDATA/IDDR2_inst/A0_S2P_1laneDATA/IDDR2_inst/IDDR2.C0Q0/FF0 (FF) Destination Clock: CLOCK_IN_0 rising at 0.000ns Requirement: 3.015ns Data Path Delay: 5.843ns (Levels of Logic = 0) Clock Path Delay: 2.871ns (Levels of Logic = 2) Clock Uncertainty: 0.000ns Maximum Data Path: DOUT0A_P to A0_S2P_1laneDATA/IDDR2_inst/A0_S2P_1laneDATA/IDDR2_inst/IDDR2.C0Q0/FF0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H3.ICLK1 Tiopickd 5.843 DOUT0A_P DOUT0A_P A0_S2P_1laneDATA/IBUFDS_inst/IBUFDS DOUT0A_P.DELAY_ADJ A0_S2P_1laneDATA/IDDR2_inst/A0_S2P_1laneDATA/IDDR2_inst/IDDR2.C0Q0/FF0 ------------------------------------------------- --------------------------- Total 5.843ns (5.843ns logic, 0.000ns route) (100.0% logic, 0.0% route) Minimum Clock Path: TCLK_P to A0_S2P_1laneDATA/IDDR2_inst/A0_S2P_1laneDATA/IDDR2_inst/IDDR2.C0Q0/FF0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- A8.I Tiopi 1.179 TCLK_P TCLK_P CLKIN_IBUFGDS_INST/IBUFDS TCLK_P.DELAY_ADJ BUFGMUX_X1Y10.I0 net (fanout=1) 0.027 CLOCK_IN_01 BUFGMUX_X1Y10.O Tgi0o 0.199 CLOCK_IN_0_BUFG CLOCK_IN_0_BUFG H3.ICLK1 net (fanout=440) 1.466 CLOCK_IN_0 ------------------------------------------------- --------------------------- Total 2.871ns (1.378ns logic, 1.493ns route) (48.0% logic, 52.0% route) -------------------------------------------------------------------------------- Hold Paths: COMP "DOUT0A_P" OFFSET = IN 3.015 ns VALID 3.125 ns BEFORE COMP "TCLK_P" "RISING"; -------------------------------------------------------------------------------- Slack (hold path): 0.764ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: DOUT0A_P (PAD) Destination: A0_S2P_1laneDATA/IDDR2_inst/A0_S2P_1laneDATA/IDDR2_inst/IDDR2.C0Q0/FF0 (FF) Destination Clock: CLOCK_IN_0 rising at 0.000ns Requirement: 0.110ns Data Path Delay: 3.916ns (Levels of Logic = 0) Clock Path Delay: 3.262ns (Levels of Logic = 2) Clock Uncertainty: 0.000ns Minimum Data Path: DOUT0A_P to A0_S2P_1laneDATA/IDDR2_inst/A0_S2P_1laneDATA/IDDR2_inst/IDDR2.C0Q0/FF0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H3.ICLK1 Tioickpd (-Th) -3.916 DOUT0A_P DOUT0A_P A0_S2P_1laneDATA/IBUFDS_inst/IBUFDS DOUT0A_P.DELAY_ADJ A0_S2P_1laneDATA/IDDR2_inst/A0_S2P_1laneDATA/IDDR2_inst/IDDR2.C0Q0/FF0 ------------------------------------------------- --------------------------- Total 3.916ns (3.916ns logic, 0.000ns route) (100.0% logic, 0.0% route) Maximum Clock Path: TCLK_P to A0_S2P_1laneDATA/IDDR2_inst/A0_S2P_1laneDATA/IDDR2_inst/IDDR2.C0Q0/FF0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- A8.I Tiopi 1.284 TCLK_P TCLK_P CLKIN_IBUFGDS_INST/IBUFDS TCLK_P.DELAY_ADJ BUFGMUX_X1Y10.I0 net (fanout=1) 0.033 CLOCK_IN_01 BUFGMUX_X1Y10.O Tgi0o 0.221 CLOCK_IN_0_BUFG CLOCK_IN_0_BUFG H3.ICLK1 net (fanout=440) 1.724 CLOCK_IN_0 ------------------------------------------------- --------------------------- Total 3.262ns (1.505ns logic, 1.757ns route) (46.1% logic, 53.9% route) --------------------------------------------------------------------------------