--- C:\MCC18\src\traditional\proc\p18F4550.asm ------------------------------------------------- 1: LIST P=18F4550 2: NOLIST 3: ;------------------------------------------------------------------------- 4: ; MPLAB-Cxx PIC18F4550 processor definition module 5: ; 6: ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved 7: ;------------------------------------------------------------------------- 8: 9: SFR_UNBANKED0 UDATA_ACS H'F62' 10: 11: SPPDATA RES 1 ; 0xF62 12: SPPCFG 13: SPPCFGbits RES 1 ; 0xF63 14: SPPEPS 15: SPPEPSbits RES 1 ; 0xF64 16: SPPCON 17: SPPCONbits RES 1 ; 0xF65 18: UFRM 19: UFRML 20: UFRMLbits RES 1 ; 0xF66 21: UFRMH 22: UFRMHbits RES 1 ; 0xF67 23: UIR 24: UIRbits RES 1 ; 0xF68 25: UIE 26: UIEbits RES 1 ; 0xF69 27: UEIR 28: UEIRbits RES 1 ; 0xF6A 29: UEIE 30: UEIEbits RES 1 ; 0xF6B 31: USTAT 32: USTATbits RES 1 ; 0xF6C 33: UCON 34: UCONbits RES 1 ; 0xF6D 35: UADDR 36: UADDRbits RES 1 ; 0xF6E 37: UCFG 38: UCFGbits RES 1 ; 0xF6F 39: UEP0 40: UEP0bits RES 1 ; 0xF70 41: UEP1 42: UEP1bits RES 1 ; 0xF71 43: UEP2 44: UEP2bits RES 1 ; 0xF72 45: UEP3 46: UEP3bits RES 1 ; 0xF73 47: UEP4 48: UEP4bits RES 1 ; 0xF74 49: UEP5 50: UEP5bits RES 1 ; 0xF75 51: UEP6 52: UEP6bits RES 1 ; 0xF76 53: UEP7 54: UEP7bits RES 1 ; 0xF77 55: UEP8 56: UEP8bits RES 1 ; 0xF78 57: UEP9 58: UEP9bits RES 1 ; 0xF79 59: UEP10 60: UEP10bits RES 1 ; 0xF7A 61: UEP11 62: UEP11bits RES 1 ; 0xF7B 63: UEP12 64: UEP12bits RES 1 ; 0xF7C 65: UEP13 66: UEP13bits RES 1 ; 0xF7D 67: UEP14 68: UEP14bits RES 1 ; 0xF7E 69: UEP15 70: UEP15bits RES 1 ; 0xF7F 71: PORTA 72: PORTAbits RES 1 ; 0xF80 73: PORTB 74: PORTBbits RES 1 ; 0xF81 75: PORTC 76: PORTCbits RES 1 ; 0xF82 77: PORTD 78: PORTDbits RES 1 ; 0xF83 79: PORTE 80: PORTEbits RES 1 ; 0xF84 81: RES 4 82: LATA 83: LATAbits RES 1 ; 0xF89 84: LATB 85: LATBbits RES 1 ; 0xF8A 86: LATC 87: LATCbits RES 1 ; 0xF8B 88: LATD 89: LATDbits RES 1 ; 0xF8C 90: LATE 91: LATEbits RES 1 ; 0xF8D 92: RES 4 93: DDRA 94: DDRAbits 95: TRISA 96: TRISAbits RES 1 ; 0xF92 97: DDRB 98: DDRBbits 99: TRISB 100: TRISBbits RES 1 ; 0xF93 101: DDRC 102: DDRCbits 103: TRISC 104: TRISCbits RES 1 ; 0xF94 105: DDRD 106: DDRDbits 107: TRISD 108: TRISDbits RES 1 ; 0xF95 109: DDRE 110: DDREbits 111: TRISE 112: TRISEbits RES 1 ; 0xF96 113: RES 4 114: OSCTUNE 115: OSCTUNEbits RES 1 ; 0xF9B 116: RES 1 117: PIE1 118: PIE1bits RES 1 ; 0xF9D 119: PIR1 120: PIR1bits RES 1 ; 0xF9E 121: IPR1 122: IPR1bits RES 1 ; 0xF9F 123: PIE2 124: PIE2bits RES 1 ; 0xFA0 125: PIR2 126: PIR2bits RES 1 ; 0xFA1 127: IPR2 128: IPR2bits RES 1 ; 0xFA2 129: RES 3 130: EECON1 131: EECON1bits RES 1 ; 0xFA6 132: EECON2 RES 1 ; 0xFA7 133: EEDATA RES 1 ; 0xFA8 134: EEADR RES 1 ; 0xFA9 135: RES 1 136: RCSTA 137: RCSTAbits RES 1 ; 0xFAB 138: TXSTA 139: TXSTAbits RES 1 ; 0xFAC 140: TXREG RES 1 ; 0xFAD 141: RCREG RES 1 ; 0xFAE 142: SPBRG RES 1 ; 0xFAF 143: SPBRGH RES 1 ; 0xFB0 144: T3CON 145: T3CONbits RES 1 ; 0xFB1 146: TMR3L RES 1 ; 0xFB2 147: TMR3H RES 1 ; 0xFB3 148: CMCON 149: CMCONbits RES 1 ; 0xFB4 150: CVRCON 151: CVRCONbits RES 1 ; 0xFB5 152: CCP1AS 153: CCP1ASbits 154: ECCP1AS 155: ECCP1ASbits RES 1 ; 0xFB6 156: CCP1DEL 157: CCP1DELbits 158: ECCP1DEL 159: ECCP1DELbits RES 1 ; 0xFB7 160: BAUDCON 161: BAUDCONbits RES 1 ; 0xFB8 162: RES 1 163: CCP2CON 164: CCP2CONbits RES 1 ; 0xFBA 165: CCPR2 166: CCPR2L RES 1 ; 0xFBB 167: CCPR2H RES 1 ; 0xFBC 168: CCP1CON 169: CCP1CONbits 170: ECCP1CON 171: ECCP1CONbits RES 1 ; 0xFBD 172: CCPR1 173: CCPR1L RES 1 ; 0xFBE 174: CCPR1H RES 1 ; 0xFBF 175: ADCON2 176: ADCON2bits RES 1 ; 0xFC0 177: ADCON1 178: ADCON1bits RES 1 ; 0xFC1 179: ADCON0 180: ADCON0bits RES 1 ; 0xFC2 181: ADRES 182: ADRESL RES 1 ; 0xFC3 183: ADRESH RES 1 ; 0xFC4 184: SSPCON2 185: SSPCON2bits RES 1 ; 0xFC5 186: SSPCON1 187: SSPCON1bits RES 1 ; 0xFC6 188: SSPSTAT 189: SSPSTATbits RES 1 ; 0xFC7 190: SSPADD RES 1 ; 0xFC8 191: SSPBUF RES 1 ; 0xFC9 192: T2CON 193: T2CONbits RES 1 ; 0xFCA 194: PR2 RES 1 ; 0xFCB 195: TMR2 RES 1 ; 0xFCC 196: T1CON 197: T1CONbits RES 1 ; 0xFCD 198: TMR1L RES 1 ; 0xFCE 199: TMR1H RES 1 ; 0xFCF 200: RCON 201: RCONbits RES 1 ; 0xFD0 202: WDTCON 203: WDTCONbits RES 1 ; 0xFD1 204: HLVDCON 205: HLVDCONbits 206: LVDCON 207: LVDCONbits RES 1 ; 0xFD2 208: OSCCON 209: OSCCONbits RES 1 ; 0xFD3 210: RES 1 211: T0CON 212: T0CONbits RES 1 ; 0xFD5 213: TMR0L RES 1 ; 0xFD6 214: TMR0H RES 1 ; 0xFD7 215: STATUS 216: STATUSbits RES 1 ; 0xFD8 217: FSR2 218: FSR2L RES 1 ; 0xFD9 219: FSR2H RES 1 ; 0xFDA 220: PLUSW2 RES 1 ; 0xFDB 221: PREINC2 RES 1 ; 0xFDC 222: POSTDEC2 RES 1 ; 0xFDD 223: POSTINC2 RES 1 ; 0xFDE 224: INDF2 RES 1 ; 0xFDF 225: BSR RES 1 ; 0xFE0 226: FSR1 227: FSR1L RES 1 ; 0xFE1 228: FSR1H RES 1 ; 0xFE2 229: PLUSW1 RES 1 ; 0xFE3 230: PREINC1 RES 1 ; 0xFE4 231: POSTDEC1 RES 1 ; 0xFE5 232: POSTINC1 RES 1 ; 0xFE6 233: INDF1 RES 1 ; 0xFE7 234: WREG RES 1 ; 0xFE8 235: FSR0 236: FSR0L RES 1 ; 0xFE9 237: FSR0H RES 1 ; 0xFEA 238: PLUSW0 RES 1 ; 0xFEB 239: PREINC0 RES 1 ; 0xFEC 240: POSTDEC0 RES 1 ; 0xFED 241: POSTINC0 RES 1 ; 0xFEE 242: INDF0 RES 1 ; 0xFEF 243: INTCON3 244: INTCON3bits RES 1 ; 0xFF0 245: INTCON2 246: INTCON2bits RES 1 ; 0xFF1 247: INTCON 248: INTCONbits RES 1 ; 0xFF2 249: PROD 250: PRODL RES 1 ; 0xFF3 251: PRODH RES 1 ; 0xFF4 252: TABLAT RES 1 ; 0xFF5 253: TBLPTR 254: TBLPTRL RES 1 ; 0xFF6 255: TBLPTRH RES 1 ; 0xFF7 256: TBLPTRU RES 1 ; 0xFF8 257: PC 258: PCL RES 1 ; 0xFF9 259: PCLATH RES 1 ; 0xFFA 260: PCLATU RES 1 ; 0xFFB 261: STKPTR 262: STKPTRbits RES 1 ; 0xFFC 263: TOS 264: TOSL RES 1 ; 0xFFD 265: TOSH RES 1 ; 0xFFE 266: TOSU RES 1 ; 0xFFF 267: 268: 269: ;*** Set all of memory to zeroes ***/ 270: ; Use FSR0 to increment through memory from address 0x0 271: ; to the end of the last data bank (no sfrs in bank). 272: 273: CODE 274: __zero_memory 00FA EE00 LFSR 0, 0 275: lfsr 0, 0 00FC F000 NOP 00FE 0E0F MOVLW 0xf 276: movlw 0xF 277: 278: clear_loop 0100 6AEE CLRF 0xfee, ACCESS 279: clrf POSTINC0, 0 0102 62EA CPFSEQ 0xfea, ACCESS 280: cpfseq FSR0H, 0 0104 D7FD BRA 0x100 281: bra clear_loop 0106 0012 RETURN 0 282: return 0 --- C:\MCC18\src\traditional\startup\c018i.c --------------------------------------------------- 1: /* $Id: c018i.c,v 1.7 2006/11/15 22:53:12 moshtaa Exp $ */ 2: 3: /* Copyright (c)1999 Microchip Technology */ 4: 5: /* MPLAB-C18 startup code, including initialized data */ 6: 7: /* external reference to __init() function */ 8: extern void __init (void); 9: /* external reference to the user's main routine */ 10: extern void main (void); 11: /* prototype for the startup function */ 12: void _entry (void); 13: void _startup (void); 14: /* prototype for the initialized data setup */ 15: void _do_cinit (void); 16: 17: extern volatile near unsigned long short TBLPTR; 18: extern near unsigned FSR0; 19: extern near char __FPFLAGS; 20: #define RND 6 21: 22: #pragma code _entry_scn=0x000000 23: void 24: _entry (void) 25: { 26: _asm goto _startup _endasm 0000 EF6F GOTO 0xde 0002 F000 NOP 27: 28: } 0004 0012 RETURN 0 29: #pragma code _startup_scn 30: void 31: _startup (void) 32: { 33: _asm 34: // Initialize the stack pointer 35: lfsr 1, _stack 00DE EE13 LFSR 0x1, 0x300 00E0 F000 NOP 36: lfsr 2, _stack 00E2 EE23 LFSR 0x2, 0x300 00E4 F000 NOP 37: 38: clrf TBLPTRU, 0 // 1st silicon doesn't do this on POR 00E6 6AF8 CLRF 0xff8, ACCESS 39: 40: bcf __FPFLAGS,RND,0 // Initialize rounding flag for floating point libs 00E8 9C01 BCF 0x1, 0x6, ACCESS 41: 42: _endasm 43: _do_cinit (); 00EA EC04 CALL 0x8, 0 00EC F000 NOP 44: 45: loop: 46: 47: // If user defined __init is not found, the one in clib.lib will be used 48: __init (); 00EE EC84 CALL 0x108, 0 00F0 F000 NOP 49: 50: // Call the user's main routine 51: main (); 00F2 EC53 CALL 0xa6, 0 00F4 F000 NOP 52: 53: goto loop; 00F6 D7FB BRA 0xee 54: } /* end _startup() */ 00F8 0012 RETURN 0 55: 56: /* MPLAB-C18 initialized data memory support */ 57: /* The linker will populate the _cinit table */ 58: extern far rom struct 59: { 60: unsigned short num_init; 61: struct _init_entry 62: { 63: unsigned long from; 64: unsigned long to; 65: unsigned long size; 66: } 67: entries[]; 68: } 69: _cinit; 70: 71: #pragma code _cinit_scn 72: void 73: _do_cinit (void) 74: { 75: /* we'll make the assumption in the following code that these statics 76: * will be allocated into the same bank. 77: */ 78: static short long prom; 79: static unsigned short curr_byte; 80: static unsigned short curr_entry; 81: static short long data_ptr; 82: 83: // Initialized data... 84: TBLPTR = (short long)&_cinit; 0008 0E06 MOVLW 0x6 000A 6EF6 MOVWF 0xff6, ACCESS 000C 0E00 MOVLW 0 000E 6EF7 MOVWF 0xff7, ACCESS 0010 0E00 MOVLW 0 0012 6EF8 MOVWF 0xff8, ACCESS 85: _asm 86: movlb data_ptr 0014 0100 MOVLB 0 87: tblrdpostinc 0016 0009 TBLRD*+ 88: movf TABLAT, 0, 0 0018 50F5 MOVF 0xff5, W, ACCESS 89: movwf curr_entry, 1 001A 6F65 MOVWF 0x65, BANKED 90: tblrdpostinc 001C 0009 TBLRD*+ 91: movf TABLAT, 0, 0 001E 50F5 MOVF 0xff5, W, ACCESS 92: movwf curr_entry+1, 1 0020 6F66 MOVWF 0x66, BANKED 93: _endasm 94: //while (curr_entry) 95: //{ 96: test: 97: _asm 98: bnz 3 0022 E103 BNZ 0x2a 99: tstfsz curr_entry, 1 0024 6765 TSTFSZ 0x65, BANKED 100: bra 1 0026 D001 BRA 0x2a 101: _endasm 102: goto done; 0028 D03D BRA 0xa4 103: /* Count down so we only have to look up the data in _cinit 104: * once. 105: * 106: * At this point we know that TBLPTR points to the top of the current 107: * entry in _cinit, so we can just start reading the from, to, and 108: * size values. 109: */ 110: _asm 111: /* read the source address */ 112: tblrdpostinc 002A 0009 TBLRD*+ 113: movf TABLAT, 0, 0 002C 50F5 MOVF 0xff5, W, ACCESS 114: movwf prom, 1 002E 6F60 MOVWF 0x60, BANKED 115: tblrdpostinc 0030 0009 TBLRD*+ 116: movf TABLAT, 0, 0 0032 50F5 MOVF 0xff5, W, ACCESS 117: movwf prom+1, 1 0034 6F61 MOVWF 0x61, BANKED 118: tblrdpostinc 0036 0009 TBLRD*+ 119: movf TABLAT, 0, 0 0038 50F5 MOVF 0xff5, W, ACCESS 120: movwf prom+2, 1 003A 6F62 MOVWF 0x62, BANKED 121: /* skip a byte since it's stored as a 32bit int */ 122: tblrdpostinc 003C 0009 TBLRD*+ 123: /* read the destination address directly into FSR0 */ 124: tblrdpostinc 003E 0009 TBLRD*+ 125: movf TABLAT, 0, 0 0040 50F5 MOVF 0xff5, W, ACCESS 126: movwf FSR0L, 0 0042 6EE9 MOVWF 0xfe9, ACCESS 127: tblrdpostinc 0044 0009 TBLRD*+ 128: movf TABLAT, 0, 0 0046 50F5 MOVF 0xff5, W, ACCESS 129: movwf FSR0H, 0 0048 6EEA MOVWF 0xfea, ACCESS 130: /* skip two bytes since it's stored as a 32bit int */ 131: tblrdpostinc 004A 0009 TBLRD*+ 132: tblrdpostinc 004C 0009 TBLRD*+ 133: /* read the destination address directly into FSR0 */ 134: tblrdpostinc 004E 0009 TBLRD*+ 135: movf TABLAT, 0, 0 0050 50F5 MOVF 0xff5, W, ACCESS 136: movwf curr_byte, 1 0052 6F63 MOVWF 0x63, BANKED 137: tblrdpostinc 0054 0009 TBLRD*+ 138: movf TABLAT, 0, 0 0056 50F5 MOVF 0xff5, W, ACCESS 139: movwf curr_byte+1, 1 0058 6F64 MOVWF 0x64, BANKED 140: /* skip two bytes since it's stored as a 32bit int */ 141: tblrdpostinc 005A 0009 TBLRD*+ 142: tblrdpostinc 005C 0009 TBLRD*+ 143: _endasm 144: //prom = data_ptr->from; 145: //FSR0 = data_ptr->to; 146: //curr_byte = (unsigned short) data_ptr->size; 147: /* the table pointer now points to the next entry. Save it 148: * off since we'll be using the table pointer to do the copying 149: * for the entry. 150: */ 151: data_ptr = TBLPTR; 005E CFF6 MOVFF 0xff6, 0x67 0060 F067 NOP 0062 CFF7 MOVFF 0xff7, 0x68 0064 F068 NOP 0066 CFF8 MOVFF 0xff8, 0x69 0068 F069 NOP 152: 153: /* now assign the source address to the table pointer */ 154: TBLPTR = prom; 006A C060 MOVFF 0x60, 0xff6 006C FFF6 NOP 006E C061 MOVFF 0x61, 0xff7 0070 FFF7 NOP 0072 C062 MOVFF 0x62, 0xff8 0074 FFF8 NOP 155: 156: /* do the copy loop */ 157: _asm 158: // determine if we have any more bytes to copy 159: movlb curr_byte 0076 0100 MOVLB 0 160: movf curr_byte, 1, 1 0078 5363 MOVF 0x63, F, BANKED 161: copy_loop: 162: bnz 2 // copy_one_byte 007A E102 BNZ 0x80 163: movf curr_byte + 1, 1, 1 007C 5364 MOVF 0x64, F, BANKED 164: bz 7 // done_copying 007E E007 BZ 0x8e 165: 166: copy_one_byte: 167: tblrdpostinc 0080 0009 TBLRD*+ 168: movf TABLAT, 0, 0 0082 50F5 MOVF 0xff5, W, ACCESS 169: movwf POSTINC0, 0 0084 6EEE MOVWF 0xfee, ACCESS 170: 171: // decrement byte counter 172: decf curr_byte, 1, 1 0086 0763 DECF 0x63, F, BANKED 173: bc -8 // copy_loop 0088 E2F8 BC 0x7a 174: decf curr_byte + 1, 1, 1 008A 0764 DECF 0x64, F, BANKED 175: bra -7 // copy_one_byte 008C D7F9 BRA 0x80 176: 177: done_copying: 178: 179: _endasm 180: /* restore the table pointer for the next entry */ 181: TBLPTR = data_ptr; 008E C067 MOVFF 0x67, 0xff6 0090 FFF6 NOP 0092 C068 MOVFF 0x68, 0xff7 0094 FFF7 NOP 0096 C069 MOVFF 0x69, 0xff8 0098 FFF8 NOP 182: /* next entry... */ 183: curr_entry--; 009A 0100 MOVLB 0 009C 0765 DECF 0x65, F, BANKED 009E 0E00 MOVLW 0 00A0 5B66 SUBWFB 0x66, F, BANKED 184: goto test; 00A2 D7BF BRA 0x22 185: done: 186: ; 187: } 00A4 0012 RETURN 0 --- C:\MCC18\src\traditional\stdclib\__init.c -------------------------------------------------- 1: 2: /** @name __init 3: * The {\bf __init} is called if the linker can not find a 4: * user defined version for it 5: */ 6: 7: void __init (void) 8: { 9: } 0108 0012 RETURN 0 --- H:\Projekte\C\Wetterstation\main.c --------------------------------------------------------- 1: /**********************************************************************************************/ 2: // Include Dateien 3: /**********************************************************************************************/ 4: 5: #include // Für den PIC - wird autom. erkannt 6: #include "delays.h" // Für die Warteschleife 7: 8: /**********************************************************************************************/ 9: // Konfiguration 10: /**********************************************************************************************/ 11: 12: #pragma config FOSC=INTOSC_HS // Taktbereich auswählen 13: #pragma config PWRT=ON // Power On Timer An 14: #pragma config WDT=OFF // 15: #pragma config BOR=OFF // Brown Out Reset Aus 16: #pragma config LVP=OFF // Low Voltage Programming Disable 17: #pragma config PBADEN=OFF // 18: #pragma config VREGEN=OFF // 19: #pragma config MCLRE=ON // Master Clear Reset An 20: 21: /**********************************************************************************************/ 22: // Globale Variablen deklarieren 23: /**********************************************************************************************/ 24: 25: unsigned int ADWERT; 26: unsigned int ADCe; 27: 28: /**********************************************************************************************/ 29: // Interruptroutinen 30: /**********************************************************************************************/ 31: /* 32: #pragma code low_vector=0x18 33: void interrupt_at_low_vector( void ) 34: { 35: _asm GOTO low_isr _endasm 36: } 37: #pragma code 38: 39: #pragma interruptlow low_isr 40: void low_isr( void ) 41: { // Low Priorität Interrupt 42: 43: } 44: 45: #pragma code high_vector=0x08 46: void interrupt_at_high_vector( void ) 47: { 48: _asm GOTO high_isr _endasm 49: } 50: #pragma code 51: 52: #pragma interruptlow high_isr 53: void high_isr( void ) 54: { // High Priorität Interrupt 55: 56: } 57: */ 58: /**********************************************************************************************/ 59: // Unterprogramme 60: /**********************************************************************************************/ 61: /* 62: void Setup_ADC(void) 63: { 64: ADCON0bits.ADON=0; 65: TRISAbits.TRISA0=1; 66: ADCON2=0x3C; 67: ADCON2bits.ADFM = 1; 68: ADCON0bits.ADON=1; 69: } 70: 71: void Read_ADC(unsigned char Channel) 72: { 73: switch(Channel) 74: { 75: case 0: 76: ADCON0bits.CHS0=0; 77: ADCON0bits.CHS1=0; 78: ADCON0bits.CHS2=0; 79: ADCON0bits.CHS3=0; 80: break; 81: case 1: 82: ADCON0bits.CHS0=1; 83: ADCON0bits.CHS1=0; 84: ADCON0bits.CHS2=0; 85: ADCON0bits.CHS3=0; 86: break; 87: case 2: 88: ADCON0bits.CHS0=0; 89: ADCON0bits.CHS1=1; 90: ADCON0bits.CHS2=0; 91: ADCON0bits.CHS3=0; 92: break; 93: case 3: 94: ADCON0bits.CHS0=1; 95: ADCON0bits.CHS1=1; 96: ADCON0bits.CHS2=0; 97: ADCON0bits.CHS3=0; 98: break; 99: case 4: 100: ADCON0bits.CHS0=0; 101: ADCON0bits.CHS1=0; 102: ADCON0bits.CHS2=1; 103: ADCON0bits.CHS3=0; 104: break; 105: case 5: 106: ADCON0bits.CHS0=1; 107: ADCON0bits.CHS1=0; 108: ADCON0bits.CHS2=1; 109: ADCON0bits.CHS3=0; 110: break; 111: case 6: 112: ADCON0bits.CHS0=0; 113: ADCON0bits.CHS1=1; 114: ADCON0bits.CHS2=1; 115: ADCON0bits.CHS3=0; 116: break; 117: case 7: 118: ADCON0bits.CHS0=1; 119: ADCON0bits.CHS1=1; 120: ADCON0bits.CHS2=1; 121: ADCON0bits.CHS3=0; 122: break; 123: case 8: 124: ADCON0bits.CHS0=0; 125: ADCON0bits.CHS1=0; 126: ADCON0bits.CHS2=0; 127: ADCON0bits.CHS3=1; 128: break; 129: case 9: 130: ADCON0bits.CHS0=1; 131: ADCON0bits.CHS1=0; 132: ADCON0bits.CHS2=0; 133: ADCON0bits.CHS3=1; 134: break; 135: case 10: 136: ADCON0bits.CHS0=0; 137: ADCON0bits.CHS1=1; 138: ADCON0bits.CHS2=0; 139: ADCON0bits.CHS3=1; 140: break; 141: case 11: 142: ADCON0bits.CHS0=1; 143: ADCON0bits.CHS1=1; 144: ADCON0bits.CHS2=0; 145: ADCON0bits.CHS3=1; 146: break; 147: case 12: 148: ADCON0bits.CHS0=0; 149: ADCON0bits.CHS1=0; 150: ADCON0bits.CHS2=1; 151: ADCON0bits.CHS3=1; 152: break; 153: default: 154: ADCON0bits.CHS0=0; 155: ADCON0bits.CHS1=0; 156: ADCON0bits.CHS2=0; 157: ADCON0bits.CHS3=0; 158: } 159: 160: ADCON0bits.GO = 1; 161: while(ADCON0bits.NOT_DONE); 162: ADWERT=ADRESH; 163: ADWERT=ADWERT<<8; 164: ADWERT=ADWERT+ADRESL; 165: 166: } 167: */ 168: /**********************************************************************************************/ 169: // Hauptprogramm 170: /**********************************************************************************************/ 171: 172: void main(void) 173: { 174: LATA = 0x00; // PORTA löschen (kann beim Start undef. Zustand annehmen) 00A6 6A89 CLRF 0xf89, ACCESS 175: LATB = 0x00; // PORTB löschen (kann beim Start undef. Zustand annehmen) 00A8 6A8A CLRF 0xf8a, ACCESS 176: LATC = 0x00; // PORTC löschen (kann beim Start undef. Zustand annehmen) 00AA 6A8B CLRF 0xf8b, ACCESS 177: LATD = 0x00; // PORTC löschen (kann beim Start undef. Zustand annehmen) 00AC 6A8C CLRF 0xf8c, ACCESS 178: LATE = 0x00; // 00AE 6A8D CLRF 0xf8d, ACCESS 179: 180: TRISA = 0x29; // 00B0 0E29 MOVLW 0x29 00B2 6E92 MOVWF 0xf92, ACCESS 181: TRISB = 0xFC; // 00B4 0EFC MOVLW 0xfc 00B6 6E93 MOVWF 0xf93, ACCESS 182: TRISC = 0x02; // 00B8 0E02 MOVLW 0x2 00BA 6E94 MOVWF 0xf94, ACCESS 183: TRISD = 0x00; // 00BC 6A95 CLRF 0xf95, ACCESS 184: TRISE = 0x00; // 00BE 6A96 CLRF 0xf96, ACCESS 185: 186: ADCON1 = 0x0F; // Alle Port Pins auf Digital gesetz 00C0 0E0F MOVLW 0xf 00C2 6EC1 MOVWF 0xfc1, ACCESS 187: 188: OSCCONbits.IRCF0=1; 00C4 88D3 BSF 0xfd3, 0x4, ACCESS 189: OSCCONbits.IRCF1=1; 00C6 8AD3 BSF 0xfd3, 0x5, ACCESS 190: OSCCONbits.IRCF2=1; 00C8 8CD3 BSF 0xfd3, 0x6, ACCESS 191: OSCCONbits.SCS1=1; 00CA 82D3 BSF 0xfd3, 0x1, ACCESS 192: OSCCONbits.SCS0=0; 00CC 90D3 BCF 0xfd3, 0, ACCESS 193: 194: CMCON=0x07; 00CE 0E07 MOVLW 0x7 00D0 6EB4 MOVWF 0xfb4, ACCESS 195: 196: // GLCD_Init(); 197: // Setup_ADC(); 198: 199: while(1); 00D2 D7FF BRA 0xd2 200: { 201: LATAbits.LATA2 = 1; // 00D4 8489 BSF 0xf89, 0x2, ACCESS 202: LATEbits.LATE0 = 1; // 00D6 808D BSF 0xf8d, 0, ACCESS 203: LATAbits.LATA4 = 1; // 00D8 8889 BSF 0xf89, 0x4, ACCESS 204: LATD=0xFF; 00DA 688C SETF 0xf8c, ACCESS 205: } 206: } 00DC 0012 RETURN 0